Memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-11829645-B2
Application number	US-202217665926-A
Country	US
Kind code	B2
Filing date	Feb 7, 2022
Priority date	Aug 27, 2019
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

First claim

What is claimed is:

1. A memory controller comprising:
a host interface configured to receive a write request and a write address from a host;
a non-volatile memory interface configured to transmit a program command along with a program mode to a non-volatile memory; and
a program mode control circuitry configured to:
detect an erase program interval (EPI) of a memory group corresponding to the write address, wherein the detected EPI is a time period from an erase time point to a program time point of the memory group, and the memory group is included in the non-volatile memory,
select the program mode, for the memory group, from a plurality of program modes, based on the detected EPI of the memory group, and
control a program operation on the memory group, based on the selected program mode, wherein controlling the program operation includes adjusting at least one voltage level associated with the program operation, based on the selected program mode.

2. The memory controller of claim 1 , wherein the plurality of program modes comprises at least one of:
a quadruple-level cell (QLC) mode, a triple level cell (TLC) mode, a multi-level cell (MLC) mode, and a single level cell (SLC) mode, or combinations thereof.

3. The memory controller of claim 1 , wherein the memory group comprises at least one of a memory block, a memory stack, and a sub-memory block, or combinations thereof.

4. The memory controller of claim 1 , wherein the program mode control circuitry is further configured to:
select the program mode, for the memory group, to be a first program mode or a second program mode, based on the detected EPI of the memory group, wherein the first program mode includes writing N-bit data to each memory cell of the memory group, and the second program mode includes writing M-bit data to each memory cell of the memory group, and
wherein N and M are positive integers, and M is less than N.

5. The memory controller of claim 1 , wherein:
the memory group includes a memory block; and
the program mode control circuitry is further configured to:
select the program mode, for the memory block, as a first program mode in which N-bit data is written to each memory cell, in response to the detected EPI of the memory group being equal to, or shorter than, a reference time, and
select the program mode, for the memory block, as a second program mode in which M-bit data is written to each memory cell, in response to the detected EPI of the memory group exceeding the reference time, and

wherein N and M are positive integers, and M is less than N.

6. The memory controller of claim 1 , wherein:
the host interface is further configured to receive a read request and a read address, corresponding to a second memory group, from the host;
the non-volatile memory interface is further configured to transmit a read command along with a read condition to the non-volatile memory, based on the read request and the read address; and
the memory controller is further configured to:
detect at least one of a second EPI of the second memory group and a second program mode of the second memory group, and
adjust the read condition for the second memory group, based on the at least one of the second EPI and the second program mode, wherein adjusting the read condition includes adjusting at least one voltage level associated with the read condition, based on the at least one of the second EPI and the second program mode.

7. The memory controller of claim 1 , wherein:
the memory controller is further configured to:
perform a garbage collection operation in order to program valid data included in a source block to a target block,
detect an EPI of the target block, and
determine a program mode for the target block, based on the detected EPI of the target block; and

the non-volatile memory interface is further configured to transmit a program command for the target block along with the program mode for the target block to the non-volatile memory.

8. The memory controller of claim 1 , further comprising:
an EPI checker circuitry configured to:
measure the EPI of the memory group during a user data program operation in response to the write request received from the host,
measure the EPI of the memory group during a meta data program operation,
measure the EPI of the memory group during a garbage collection operation, or
combinations thereof.

9. A non-volatile memory comprising:
a memory cell array including a plurality of memory blocks, each memory block of the plurality of memory blocks including a plurality of memory stacks stacked on a substrate in a perpendicular direction to the substrate, the plurality of memory stacks including a first memory stack and a second memory stack located above the first memory stack in the perpendicular direction; and
control circuitry configured to perform a program operation, for the first memory stack, based on a first program mode corresponding to the first memory stack, and perform a program operation, for the second memory stack, based on a second program mode corresponding to the second memory stack,
wherein the control circuitry is further configured to:
select the first program mode, based on a first erase program interval (EPI) of the first memory stack, wherein the first EPI is a time period from an erase time point to a program time point of the first memory stack, and
select the second program mode, based on a second EPI of the second memory stack, wherein the second EPI is a time period from an erase time point to a program time point of the second memory stack.

10. The non-volatile memory of claim 9 , wherein the control circuitry is further configured to select the second program mode in response to the first EPI exceeding a reference time during a program operation performed on the first memory stack.

11. The non-volatile memory of claim 9 , wherein:
the first program mode corresponds to at least one of a quadruple-level cell (QLC) mode, a triple level cell (TLC) mode, a multi-level cell (MLC) mode, and a single level cell (SLC) mode, based on the first EPI; and
the second program mode corresponds to at least one of the QLC mode, the TLC mode, the MLC mode, and the SLC mode, based on the second EPI.

12. The non-volatile memory of claim 9 , wherein the control circuitry is further configured to receive the first program mode and the second program mode from a memory controller.

13. The non-volatile memory of claim 9 , further comprising:
an EPI checker circuitry configured to measure the first EPI and the second EPI, and
wherein the control circuitry is further configured to receive EPI information from the EPI checker circuitry, determine a program mode, based on the received EPI information, and control a program operation on the memory cell array according to the determined program mode.

14. The non-volatile memory of claim 9 , further comprising:
an EPI checker circuitry configured to measure the first EPI and the second EPI, and
wherein the control circuitry is further configured to receive EPI information from the EPI checker circuitry, determine a read condition, based on the received EPI information, and control a read operation on the memory cell array according to the determined read condition.

15. A non-volatile memory comprising:
a memory cell array including a plurality of memory blocks, each memory block of the plurality of memory blocks including a plurality of sub-memory blocks that are independently erasable, the plurality of sub-memory blocks including a first sub-memory block and a second sub-memory block; and
control circuitry co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Jaeduk
• Lim Bongsoon
• Choi Yonghyuk

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title