Filter apparatus for semiconductor device fabrication process

US11826709B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11826709-B2
Application numberUS-202117333499-A
CountryUS
Kind codeB2
Filing dateMay 28, 2021
Priority dateMay 28, 2021
Publication dateNov 28, 2023
Grant dateNov 28, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A filter device includes one or more filter membranes, and a filter housing enclosing the one or more filter membranes. Each of the filter membranes includes a base membrane and a plurality of through holes.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a filter membrane, the method comprising: forming a photo resist layer over a substrate; forming a polymer layer over the photo resist layer; patterning the polymer layer to form a plurality of through holes in the polymer layer; removing the polymer layer with the plurality of through holes from the substrate, thereby obtaining the filter membrane; and forming a coating layer made of a polymer material over the filter membrane to reduce diameters of the through holes, wherein: the patterning comprises: placing a hard mask over the polymer layer not to contact the polymer layer and at a distance of 1 μm to 1 mm from the polymer layer, the hard mask including a plurality of through holes and being made of a ceramic material; etching the polymer layer by plasma passing through the plurality of through holes formed in the hard mask; and an average diameter of the plurality of through holes after the diameters are reduced is in a range from 5 nm to 50 nm. 2. The method of claim 1 , wherein an aspect ratio of plurality of through holes in the polymer layer is in a range from 2 to 10. 3. The method of claim 1 , wherein the polymer layer includes one or more of PVDF (polyvinylidene fluoride), PFA (polyfluoroalkyl), PAS (polyarylsulfone), PES(polyether sulfone), and PEEK (polyetheretherketone), or derivatives thereof. 4. The method of claim 1 , wherein the polymer material of the coating layer is different from the polymer layer. 5. The method of claim 4 , wherein the polymer material of the coating layer is PTFE (polytetrafluoroethylene). 6. The method of claim 1 , wherein a total number of the plurality of holes per square micron in the polymer layer is in a range from 100 to 600. 7. A method of manufacturing a filter membrane, the method comprising: forming a photo resist layer over a substrate; forming a polymer layer over the photo resist layer; placing a hard mask over the polymer layer not to contact the polymer layer and at a distance of 1 μm to 1 mm from the polymer layer, the hard mask including a plurality of through holes and being made of a ceramic material; and etching the polymer layer by plasma passing through the plurality of through holes formed in the hard mask, thereby forming a plurality of through holes in the polymer layer; and removing the polymer layer with the plurality of through holes from the substrate, thereby obtaining the filter membrane. 8. The method of claim 7 , wherein the hard mask is made of ceramic. 9. The method of claim 7 , wherein the hard mask is made of anodic aluminum oxide. 10. The method of claim 7 , wherein the plasma is generated from one or more gases including C 4 F 8 , SF 6 , O 2 or Ar. 11. The method of claim 7 , further comprising attaching a fiber based filter membrane to the filter membrane. 12. The method of claim 11 , wherein the fiber based filter membrane has random hole sizes. 13. A method of manufacturing a filter membrane, the method comprising: forming a sacrificial layer over a substrate; forming a polymer layer over the sacrificial layer; placing a hard mask over the polymer layer not to contact the polymer layer and at a distance of 1 μm to 1 mm from the polymer layer, the hard mask including a plurality of through holes and being made of a ceramic material; and etching the polymer layer by plasma passing through the plurality of through holes formed in the hard mask, thereby forming a plurality of through holes in the polymer layer; and removing the polymer layer with the plurality of through holes from the substrate, thereby obtaining the filter membrane. 14. The method of claim 13 , further comprising forming a coating layer made of a polymer material over the filter membrane to reduce diameter of the through holes, wherein the coating material comprises a polymer. 15. The method of claim 14 , wherein the polymer of the coating material is different from the polymer layer. 16. The method of claim 14 , wherein the polymer of the coating material is a same as the polymer layer. 17. The method of claim 1 , wherein a surface of the hard mask is coated with a coating material. 18. The method of claim 17 , wherein the coating material is silicon oxide or silicon nitride. 19. The method of claim 1 , wherein the polymer layer includes one or more of PFA (polyfluoroalkyl), PAS (polyarylsulfone), PES(polyether sulfone), or derivatives thereof. 20. The method of claim 7 , wherein the polymer layer includes one or more of PFA (polyfluoroalkyl), PAS (polyarylsulfone), PES(polyether sulfone), or derivatives thereof.

Assignees

Inventors

Classifications

  • Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title

  • Details relating to pores or porosity of the membranes · CPC title

  • Flat membrane modules · CPC title

  • Flat membranes · CPC title

  • by micromachining techniques, e.g. using masking and etching steps, photolithography · CPC title

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Frequently asked questions

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What does patent US11826709B2 cover?
A filter device includes one or more filter membranes, and a filter housing enclosing the one or more filter membranes. Each of the filter membranes includes a base membrane and a plurality of through holes.
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification B01D67/0034. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Nov 28 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).