Ferroelectric nonvolatile memory device and integration schemes

Patent metadata

Field	Value
Publication number	US-11825663-B2
Application number	US-202117403880-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Aug 17, 2021
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.

First claim

What is claimed:

1. A nonvolatile memory device comprising:
a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, wherein the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor; and
a metallization layer arranged over the ferroelectric memory capacitor, wherein the metallization layer directly contacts a top surface of the ferroelectric memory capacitor, the metallization layer is a word line.

2. The nonvolatile memory device of claim 1 , wherein the gate contact of the second transistor and a portion of a gate of the second transistor are next to the first active region contact of the first transistor.

3. The nonvolatile memory device of claim 2 , wherein an active region of the first transistor is arranged perpendicular to the gate of the second transistor.

4. The nonvolatile memory device of claim 2 , wherein the gate of the first transistor is parallel to the gate of the second transistor.

5. The nonvolatile memory device of claim 2 , further comprising:
an active region of the second transistor, wherein the gate of the second transistor is arranged over the active region of the second transistor; and
a first active region contact of the second transistor is arranged between the gate of the first transistor and the gate of the second transistor.

6. The nonvolatile memory device of claim 5 , wherein the active region of the second transistor is spaced apart from the ferroelectric memory capacitor.

7. The nonvolatile memory device of claim 5 , wherein the first active region contact of the second transistor is connected to a bit line and a second active region contact of the second transistor is connected to a source line.

8. The nonvolatile memory device of claim 1 , further comprising:
a second active region contact of the first transistor, wherein the second active region contact is laterally spaced apart from the ferroelectric memory capacitor, the ferroelectric memory capacitor does not overlap the second active region contact.

9. The nonvolatile memory device of claim 8 , wherein the second active region contact of the first transistor is connected to a program line.

10. The nonvolatile memory device of claim 1 , further comprising:
a liner material over a side surface of the ferroelectric memory capacitor.

11. An array of nonvolatile memory devices comprising:
a first ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, wherein the first ferroelectric memory capacitor at least partially overlaps a gate of the first transistor;
a second ferroelectric memory capacitor arranged adjacent to the first ferroelectric memory capacitor, wherein the second ferroelectric memory capacitor is arranged over an active region contact of a third transistor and a gate contact of a fourth transistor, and the second ferroelectric memory capacitor at least partially overlaps a gate of the third transistor;
a metallization layer arranged over the first ferroelectric memory capacitor and the second ferroelectric memory capacitor, wherein the metallization layer directly contacts a top surface of the first ferroelectric memory capacitor, the gate of the third transistor is a gate of a fifth transistor, and the gate of the third transistor and the fifth transistor extends over an active region of the third transistor and an active region of the fifth transistor; and
an active region of the second transistor, wherein a gate of the second transistor and a gate of the fourth transistor are arranged over the active region of the second transistor.

12. The array of nonvolatile memory devices of claim 11 , further comprising:
a source contact over the active region of the second transistor between the gate of the second transistor and the gate of the fourth transistor.

13. The array of nonvolatile memory devices of claim 11 , wherein the metallization layer is a word line.

14. The array of nonvolatile memory devices of claim 11 , wherein a spacing between the active region of the third transistor and the active region of the fifth transistor is at least half that of a spacing between the active region of the second transistor and the active region of the third transistor.

15. The array of nonvolatile memory devices of claim 11 , further comprising:
a third ferroelectric memory capacitor arranged adjacent to the second ferroelectric memory capacitor, wherein the third ferroelectric memory capacitor at least partially overlaps the gate of the fifth transistor.

16. The array of nonvolatile memory devices of claim 15 , wherein the gate of the first transistor is a gate of a seventh transistor and a fourth ferroelectric memory capacitor is arranged adjacent to the first ferroelectric memory capacitor and the third ferroelectric memory capacitor, wherein the fourth ferroelectric memory capacitor at least partially overlap the gate of the seventh transistor.

17. A method of fabricating a nonvolatile memory device comprising:
forming a gate of a first transistor;
forming a first active region contact of the first transistor;
forming a gate contact of a second transistor; and
forming a ferroelectric memory capacitor over the first active region contact of the first transistor and the gate contact of the second transistor, wherein the ferroelectric memory capacitor at least partially overlaps the gate of the first transistor; and
forming a metallization layer over the ferroelectric memory capacitor, wherein the metallization layer directly contacts a top surface of the ferroelectric memory capacitor, the metallization layer is a word line.

18. The method of claim 17 , wherein the formation of the ferroelectric memory capacitor further comprises:
forming a bottom electrode layer over the first active region contact of the first transistor and the gate contact of the second transistor; and
forming a ferroelectric layer over the bottom electrode layer and a top electrode layer over the ferroelectric layer.

19. The method of claim 18 , wherein the metallization layer and the first active region contact of the first transistor are made of different materials.

Assignees

• Globalfoundries Us Inc

Inventors

• MüLLER JOHANNES
• Melde Thomas
• Dünkel Stefan
• Richter Ralf

Classifications

• H10B53/30 Primary

  characterised by the memory core region · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• H10B53/10

  characterised by the top-view layout · CPC title