Semiconductor device and array layout thereof and package structure comprising the same

Patent metadata

Field	Value
Publication number	US-11825653-B2
Application number	US-202016923144-A
Country	US
Kind code	B2
Filing date	Jul 8, 2020
Priority date	Dec 23, 2019
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first portion and a second portion of the channel layer. The first portion is opposite to the second portion. The first portion is surrounded by the memory structure, and the second portion is exposed from the memory structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a stack formed on a substrate, the stack including a plurality of conductive layers and a plurality of insulating layers alternately stacked with the conductive layers; and
a plurality of memory strings penetrating the stack along a first direction, and each of the memory strings having a first side and a second side opposite to each other along a second direction perpendicular to the first direction, and comprising
a channel layer extending along the first direction;
a memory structure disposed between the stack and the channel layer on the first side; and
a first conductive pillar and a second conductive pillar extending along the first direction and electrically isolated from each other, and respectively coupled to a first portion and a second portion of the channel layer, and the first portion is opposite to the second portion along the second direction, wherein the memory structure extends along an outer surface of the channel layer to surround the first portion on the first side and stops extending to the second portion on the second side.

2. The semiconductor device according to claim 1 , wherein:
the channel layer has an annular cross section along the second direction and a third direction, the second direction and the third direction are perpendicular to the first direction, the channel layer has an annular inner surface, the first conductive pillar and the second conductive pillar are coupled to the annular inner surface.

3. The semiconductor device according to claim 1 , wherein each of the memory strings comprises an insulating pillar disposed in a central area.

4. The semiconductor device according to claim 3 , wherein the first conductive pillar and the second conductive pillar are connected to the insulating pillar.

5. The semiconductor device according to claim 1 , further comprising:
a plurality of input lines, one of the input lines is coupled to the first conductive pillar; and
a plurality of output lines, one of the output lines is coupled to the second conductive pillar.

6. The semiconductor device according to claim 5 , wherein the input lines and the output lines are parallel to each other and extend along the second direction.

7. The semiconductor device according to claim 1 , further comprising a plurality of isolation trenches dividing the stack into a plurality of sub-stacks, wherein each of the isolation trenches extends in a direction perpendicular to an extending direction of a connection line between the first conductive pillar and the second conductive pillar.

8. The semiconductor device according to claim 1 , further comprising a plurality of isolation trenches dividing the stack into a plurality of sub-stacks, wherein each of the isolation trenches extends in a direction parallel to an extending direction of a connection line between the first conductive pillar and the second conductive pillar.

9. The semiconductor device according to claim 1 , wherein the memory structure comprises a charge storage material.

10. The semiconductor device according to claim 1 , wherein the memory structure includes a ferroelectric material.

11. The semiconductor device according to claim 1 , wherein each of the memory strings has an oval cross section.

12. The semiconductor device according to claim 1 , wherein at least one conductive layer of the conductive layers comprises a first gate and a second gate, the first gate and the second gate are separated from each other by an isolation structure, the first gate corresponds to the first portion, and the second gate corresponds to the second-portion.

13. The semiconductor device according to claim 12 , wherein the first gate is used as a memory gate and the second gate is used as a selection gate.

14. The semiconductor device according to claim 12 , further comprising an oxide layer, wherein the oxide layer is disposed between the channel layer and the second gate, and the memory structure is disposed between the channel layer and the first gate.

15. The semiconductor device according to claim 14 , wherein the oxide layer extends between the channel layer and the second gate, and between the isolation structure and the second gate; the memory structure extends between the isolation structure and the first gate, and between the channel layer and the first gate.

16. The semiconductor device according to claim 12 , wherein portions of the isolation structure corresponding to the insulating layers above the first gate and the second gate have a first width along the second direction; portions of the isolation structure correspond to the first gate and the second gate have a second width along the second direction, the first width is greater than the second width.

17. An array layout of a semiconductor device, comprising:
a stack formed on a substrate, the stack including a plurality of conductive layers and a plurality of insulating layers alternately stacked with the conductive layers; and
a plurality of memory strings penetrating the stack along a first direction and disposed on the substrate as a memory array along a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other, each of the memory strings has a first side and a second side opposite to each other along the second direction and comprises:
a channel layer extending along the first direction;
a memory structure disposed between the stack and the channel layer on the first side; and
a first conductive pillar and a second conductive pillar extending along the first direction and electrically isolated from each other, and respectively coupled to a first portion and a second portion of the channel layer, and the first portion is opposite to the second portion along the second direction, wherein the memory structure extends along an outer surface of the channel layer to surround the first portion on the first side and stops extending to the second portion on the second side,
the memory strings are disposed into a plurality of rows of the memory strings along the third direction in the memory array, and adjacent rows of the memory strings have an offset distance in the third direction,
wherein a plurality of the first portions of the adjacent rows of the memory strings are adjacent to each other.

18. The array layout of the semiconductor device according to claim 17 , further comprising:
a plurality of conductive patterns electrically connected to one of the first conductive pillar and the second conductive pillar;
a plurality of input lines extending along the second direction, wherein each of the input lines is coupled to the first conductive pillar that corresponds through a first via; and
a plurality of output lines extending along the second direction, wherein each of the output lines is coupled to the second conductive pillar that corresponds through a second via.

19. A package structure, comprising:
a memory chip comprising the semiconductor device according to claim 1 ; and
a memory control chip for controlling the memory chip,
wherein the memory chip is disposed on the memory control chip.

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting
• Chen Wei-Chen

Classifications

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D62/112

  for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers · CPC title