Transmission line structures for millimeter wave signals

Patent metadata

Field	Value
Publication number	US-11824249-B2
Application number	US-202218058383-A
Country	US
Kind code	B2
Filing date	Nov 23, 2022
Priority date	Mar 14, 2019
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

First claim

What is claimed is:

1. A coplanar waveguide structure, comprising:
a substrate;
a dielectric layer disposed over at least a portion of the substrate; and
a planar transmission line disposed within the dielectric layer, the planar transmission line comprising:
a conductive stacked signal line;
a first stacked ground line positioned on a first side of the conductive stacked signal line and separated from the conductive stacked signal line by a first distance; and
a second stacked ground line positioned on a second side of the conductive stacked signal line and separated from the conductive stacked signal line by a second distance,
wherein:
the conductive stacked signal line, the first stacked ground line, and the second stacked ground line each comprise a plurality of conductive segments in a plurality of conductive layers stacked vertically and electrically connected to one another with vias in via layers;
a first bottom conductive segment of the conductive stacked signal line, second bottom conductive segment of the first stacked ground line, and a third bottom conductive segment of the second stacked ground line are formed in a first conductive layer that is directly on a top surface of the substrate;
a first top conductive segment of the conductive stacked signal line, a second top conductive segment of the first stacked ground line, and a third top conductive segment of the second stacked ground line are formed in a conductive layer that is below a top conductive layer; and
the top conductive layer is an ultra-thick metal layer having a thickness of one to fifty micrometers and is not used for the conductive stacked signal line, the first stacked ground line, and the second stacked ground line.

2. The coplanar waveguide structure of claim 1 , wherein the plurality of conductive layers includes conductive layers C 1 through C N and the via layers include via layers V 1 through V M , where N is a number greater than one, M is a number equal to or greater than one, and M is less than N.

3. The coplanar waveguide structure of claim 1 , comprising a first width of the conductive stacked signal line, a second width of the first stacked ground line, and a third width of the second stacked ground line based at least in part on the number of the plurality of conductive layers formed underneath the ultra-thick metal layer.

4. The coplanar waveguide structure of claim 3 , wherein the first width of the conductive stacked signal line equals the second width of the first stacked ground line and the third width of the second stacked ground line.

5. The coplanar waveguide structure of claim 1 , wherein the plurality of conductive segments in the conductive stacked signal line and in the first stacked ground line and in the second stacked ground line are formed of copper, silver, or aluminum.

6. The coplanar waveguide structure of claim 1 , wherein the substrate is a high resistivity substrate.

7. The coplanar waveguide structure of claim 6 , wherein the high resistivity substrate includes a high resistivity silicon substrate.

8. The coplanar waveguide structure of claim 1 , wherein the first distance equals the second distance.

9. The coplanar waveguide structure of claim 1 , comprising:
a first segment of the top conductive layer situated over the conductive stacked signal line and not used by the conductive stacked signal line;
a second segment of the top conductive layer situated over the first stacked ground line and not used by the first stacked ground line; and
a third segment of the top conductive layer situated over the second stacked ground line and not used by the second stacked ground line.

10. An integrated circuit, comprising:
a coplanar waveguide structure comprising:
a substrate;
a dielectric layer disposed over at least a portion of the substrate; and
a planar transmission line disposed within the dielectric layer, wherein the planar transmission line comprises:
a conductive stacked signal line;
a first stacked ground line positioned on a first side of the conductive stacked signal line and separated from the conductive stacked signal line by a first distance; and
a second stacked ground line positioned on a second side of the conductive stacked signal line and separated from the conductive stacked signal line by a second distance,
wherein:
the conductive stacked signal line, the first stacked ground line, and the second stacked ground line each comprise a plurality of conductive segments in a plurality of conductive layers stacked vertically and electrically connected to one another with vias in via layers;
the conductive layers include conductive layers C 1 through C N and the via layers include via layers V 1 through V M , where N is a number greater than one, M is a number equal to or greater than one, and M is less than N;
a first conductive segment of the conductive stacked signal line, a second bottom conductive segment of the first stacked ground line, and a third bottom conductive segment of the second stacked ground line formed in the first conductive layer C 1 that is directly on a top surface of the high resistively substrate;
a first top conductive segment of the conductive stacked signal line, a second top conductive segment of the first stacked ground line, and a third top conductive segment of the second stacked ground line are formed in the Nth conductive layer C N that is immediately below a top conductive layer; and
the top conductive layer is an ultra-thick metal layer having a thickness of one to fifty micrometers and is not used for the conductive stacked signal line, the first stacked ground line, and the second stacked ground line.

11. The integrated circuit of claim 10 , wherein the substrate is a high resistivity substrate.

12. The integrated circuit of claim 10 , wherein a first width of the conductive stacked signal line, a second width of the first stacked ground line, and a third width of the second stacked ground line are based at least in part on the number of conductive layers formed underneath the ultra-thick metal layer.

13. The integrated circuit of claim 12 , wherein the first width of the conductive stacked signal line equals the second width of the first stacked ground line and the third width of the second stacked ground line.

14. The integrated circuit of claim 10 , wherein the first distance equals the second distance.

15. The integrated circuit of claim 10 , comprising:
a first segment of the top conductive layer situated over the conductive stacked signal line and not used by the conductive stacked signal line;
a second segment of the top conductive layer situated over the first stacked ground line and not used by the first stacked ground line; and
a third segment of the top conductive layer situated over the second stacked ground line and not used by the second stacked ground line.

16. A method for fabricating a stacked signal line and stacked ground lines for a planar transmission line, the method comprising:
forming a first conductive layer directly on a substrate;
patterning the first conductive layer to form a first conductive segment for the stacked signal line and second conductive segments for the stacked ground lines;
forming a dielectric material over and between the first and the second conductive segments;
forming a first opening in the dielectric material for a first via to be formed on the first conductive segment and second openings for second vias to be formed on the second conductive segments;
filling the first and the second openings with a conductive material;
forming and pat

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jin Jun-De

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H01P3/003 Primary

  Coplanar lines · CPC title

• H01L23/66

  Electricity · mapped topic