Wiring substrate and semiconductor device each having first and second via wirings

Patent metadata

Field	Value
Publication number	US-11823993-B2
Application number	US-202117508944-A
Country	US
Kind code	B2
Filing date	Oct 22, 2021
Priority date	Oct 28, 2020
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.

First claim

What is claimed is:

1. A wiring substrate, comprising:
a first insulation layer;
a first through hole extending through the first insulation layer in a thickness-wise direction;
a first via wiring formed in the first through hole;
a second insulation layer formed on an upper surface of the first insulation layer;
a first recess formed in a lower surface of the second insulation layer and connected to the first through hole;
an opening formed in an upper surface of the second insulation layer and connected to the first recess;
a second recess formed in an upper surface of the first via wiring and connected to the first recess;
a second via wiring formed in the opening, the first recess, and the second recess;
a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring;
a second wiring pattern formed in the first recess and electrically connected to the first via wiring; and
a second through hole extending through the second wiring pattern in the thickness-wise direction and connected to the opening and the second recess,
wherein the second via wiring fills the opening, the second through hole, and the second recess.

2. The wiring substrate according to claim 1 , wherein the second insulation layer and the first insulation layer differ from each other in thermal expansion coefficient, and an interface between the first via wiring and a lower end surface of the second via wiring is located at a lower position than an interface between the first insulation layer and the second insulation layer.

3. The wiring substrate according to claim 1 , wherein an upper end of the second through hole has a larger opening width than a lower end of the opening.

4. The wiring substrate according to claim 3 , wherein a lower end of the second through hole has a larger opening width than an upper end of the first through hole.

5. The wiring substrate according to claim 3 , wherein a lower end of the second through hole has a smaller opening width than an upper end of the first through hole, and a wall surface of the second recess is continuous with a wall surface of the second through hole.

6. The wiring substrate according claim 1 , wherein the second via wiring includes
an upper via part formed in the opening and extending from a position of the upper surface of the second insulation layer to an intermediate position of the second insulation layer,
an intermediate via part integrated with the upper via part and formed in at least a portion of the first recess and extending from the intermediate position of the second insulation layer to a position of a lower surface of the second insulation layer, the intermediate via part including an anchor extending sideward from a lower end of the upper via part to an inner side of the second insulation layer, and
a lower via part integrated with the intermediate via part and formed in the second recess and extending downward from a position of the upper surface of the first insulation layer, the lower via part being in contact with the upper surface of the first via wiring.

7. The wiring substrate according to claim 6 , wherein the upper via part, the intermediate via part, and the lower via part are integrated to be generally cross-shaped in a cross-sectional view.

8. The wiring substrate according to claim 6 , wherein the upper via part, the intermediate via part, and the lower via part are integrated to be generally inverted-T-shaped in a cross-sectional view.

9. A wiring substrate, comprising:
a first insulation layer;
a first through hole extending through the first insulation layer in a thickness-wise direction;
a first via wiring formed in the first through hole;
a second insulation layer formed on an upper surface of the first insulation layer;
a first recess formed in a lower surface of the second insulation layer and connected to the first through hole;
an opening formed in an upper surface of the second insulation layer and connected to the first recess;
a second recess formed in an upper surface of the first via wiring and connected to the first recess;
a second via wiring formed in the opening, the first recess, and the second recess; and
a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring, wherein
the second insulation layer and the first insulation layer differ from each other in thermal expansion coefficient, and
an interface between the first via wiring and a lower end surface of the second via wiring is located at a lower position than an interface between the first insulation layer and the second insulation layer.

10. A semiconductor device, comprising:
the wiring substrate according to claim 1 ; and
a semiconductor element mounted on the wiring substrate, wherein
the second insulation layer includes a solder resist layer,
the first wiring pattern includes a rod-shaped connection terminal extending upward from an upper surface of the solder resist layer, and
the semiconductor element is connected to the first wiring pattern.

Assignees

• Shinko Electric Ind Co

Inventors

• Muroga Masataka

Classifications

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/072

  of bump connectors · CPC title