Array substrate, fabrication method thereof, liquid crystal display panel and display device

Patent metadata

Field	Value
Publication number	US-11822178-B2
Application number	US-202016835824-A
Country	US
Kind code	B2
Filing date	Mar 31, 2020
Priority date	Oct 17, 2019
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

Disclosed are an array substrate, a fabrication method thereof, a liquid crystal display panel and a display device. The array substrate includes a substrate, a wire grid polarization layer located in an open region in a pixel region of the substrate and a transparent pattern located at the side, away from the substrate, of the wire grid polarization layer and consistent with a pattern of the wire grid polarization layer.

First claim

The invention claimed is:

1. An array substrate, comprising a substrate, a wire grid polarization layer located in an open region in a pixel region of the substrate and a transparent pattern located at a side, away from the substrate, of the wire grid polarization layer and consistent with a pattern of the wire grid polarization layer;
wherein the wire grid polarization layer comprises a plurality of metal wires, and slits are formed between the metal wires; and the array substrate further comprises:
filler located in the slits, wherein the filler and the transparent pattern are of an integrated structure; a material of the filler is indium tin oxide or indium zinc oxide;
wherein the filler comprises a first subsection in contact with a metal wire at one side of the slit where the filler is located, a second subsection in contact with a metal wire at the other side of the slit where the filler is located and a third subsection connecting the first subsection with the second subsection;
a gap is formed between the first subsection and the second subsection; and
the third subsection is in contact with the substrate.

2. The array substrate of claim 1 , further comprising a silicon dioxide layer located between the metal wires and the transparent pattern; and
an orthographic projection of the silicon dioxide layer on the substrate being mutually overlaps with orthographic projections of the metal wires on the substrate.

3. The array substrate of claim 1 , further comprising a transistor located in a non-open region in the pixel region and an electrode structure located at a side, away from the wire grid polarization layer, of a layer where the transparent pattern is located;
the wire grid polarization layer being reused as a common electrode, and the electrode structure being a pixel electrode electrically connected with a drain electrode of the transistor;
or the wire grid polarization layer being reused as a pixel electrode and being electrically connected with the drain electrode of the transistor, and the electrode structure being a common electrode.

4. A fabrication method of an array substrate, comprising:
providing a substrate;
forming a wire grid polarization layer on a whole surface of the substrate;
forming a transparent pattern consistent with a pattern of the wire grid polarization layer on the wire grid polarization layer located in an open region in a pixel region of the substrate; and
etching the wire grid polarization layer by taking the transparent pattern as a mask;
wherein the wire grid polarization layer comprises a plurality of metal wires, and slits are formed between the metal wires, when forming the transparent pattern consistent with a pattern of the wire grid polarization layer, the method further comprises:
forming filler filling the slits, wherein the filler and the transparent pattern are of an integrated structure; a material of the filler is indium tin oxide or indium zinc oxide;
wherein the forming the filler filling the slits when forming the transparent pattern consistent with the pattern of the wire grid polarization layer comprises:
forming a transparent material layer covering the metal wires, wherein gaps are formed between the transparent material layers in a same slit or between the transparent material layers in a same slit are in contact with each other;
coating the transparent material layers in the open region in the pixel region with a photoresist; and
etching the transparent material layers by taking the photoresist as a mask to form the transparent pattern with an orthographic projection overlapping with the metal wires and the filler filling the slits, wherein
the filler comprises a first subsection in contact with the metal wire at one side of the slit where the filler is located, a second subsection in contact with the metal wire at other side of the slit where the filler is located and a third subsection connecting the first subsection with the second subsection; a gap is formed between the first subsection and the second subsection; the third subsection is in contact with the substrate.

5. The fabrication method of claim 4 , wherein the etching the wire grid polarization layer by taking the transparent pattern as the mask comprises:
etching the wire grid polarization layer by taking the transparent pattern and the filler as masks.

6. The fabrication method of claim 5 , wherein before etching the wire grid polarization layer by taking the transparent pattern and the filler as the masks, the method further comprises:
performing a stripping treatment on the photoresist; and
performing an annealing treatment on the transparent pattern and the filler.

7. The fabrication method of claim 4 , wherein the etching the transparent material layers by taking the photoresist as the mask comprises:
etching the transparent material layers by taking the photoresist as the mask and adopting a wet etching process.

8. A liquid crystal display panel, comprising an array substrate and an opposite substrate arranged oppositely, wherein
the array substrate is the array substrate of claim 1 .

9. A display device, comprising the liquid crystal display panel of claim 8 .

10. An array substrate, comprising a substrate, a wire grid polarization layer located in an open region in a pixel region of the substrate and a transparent pattern located at a side, away from the substrate, of the wire grid polarization layer and consistent with a pattern of the wire grid polarization layer;
wherein the wire grid polarization layer comprises a plurality of metal wires, and slits are formed between the metal wires; and the array substrate further comprises:
filler located in the slits, wherein the filler and the transparent pattern are of an integrated structure; a material of the filler is indium tin oxide or indium zinc oxide;
wherein the filler comprises a first subsection in contact with a metal wire at one side of the slit where the filler is located, a second subsection in contact with a metal wire at the other side of the slit where the filler is located and a third subsection connecting the first subsection with the second subsection;
the third subsection is in contact with the substrate;
wherein the slits are completely filled with the filler.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Im Yunsik
• Choi Hyunsic
• Hou Kai

Classifications

• G02F1/133528 Primary

  Polarisers · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/13625

  Patterning using multi-mask exposure · CPC title

• G02F1/133548 Primary

  Wire-grid polarisers · CPC title

• G02F1/136295

  Materials; Compositions; Manufacture processes · CPC title