Electro-optical phase modulator

Patent metadata

Field	Value
Publication number	US-11822164-B2
Application number	US-202017009468-A
Country	US
Kind code	B2
Filing date	Sep 1, 2020
Priority date	Jan 15, 2018
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.

First claim

The invention claimed is:

1. A method, comprising:
etching a semiconductor layer of a silicon-on-insulator (SOI) substrate to form a first strip portion of a waveguide comprising a first region having a first thickness and a second region having a second thickness that is smaller than the first thickness;
covering the first strip portion with an insulating material;
forming an opening in the insulating material that exposes an upper surface of the first region, with the insulating material remaining at a bottom of the opening sufficient to cover an upper surface of second region;
covering the exposed upper surface of the first region with a first insulating layer;
forming a second strip portion of the waveguide on the first insulating layer and on the insulating material at the bottom of the opening;
covering an upper surface of the second strip portion with a second insulating layer; and
forming a third strip portion of the waveguide on the second insulating layer and on the insulating material at the bottom of the opening.

2. The method of claim 1 , wherein the waveguide is an electro-optical phase modulator, and further comprising:
making a first electrical contact to the first strip portion;
making a second electrical contact to the second strip portion; and
making a third electrical contact to third strip portion.

3. The method of claim 2 , wherein etching the semiconductor layer of the silicon-on-insulator (SOI) substrate further forms a third region of the first strip portion of the waveguide, and wherein making the first electrical contact comprises making contact with the third region.

4. The method of claim 3 , wherein the third region has a third thickness that is greater than the first thickness and greater than the second thickness.

5. The method of claim 2 , wherein making the first, second and third electrical contacts comprises forming a silicide contact.

6. The method of claim 1 , wherein the second strip portion of the waveguide on the insulating material at the bottom of the opening is located on one side of the first region of the first strip portion and the third strip portion of the waveguide on the insulating material at the bottom of the opening is located on another side of the first region of the first strip portion opposite said one side.

7. The method of claim 6 , wherein the third strip portion of the waveguide on the insulating material at the bottom of the opening extends over the second region of the first strip portion.

8. The method of claim 1 , wherein the insulating material is a silicon oxide material.

9. The method of claim 1 , wherein the semiconductor layer of the SOI substrate is single crystal semiconductor material.

10. The method of claim 9 , wherein the second strip portion of the waveguide is doped polysilicon material.

11. The method of claim 9 , wherein the third strip portion of the waveguide is doped polysilicon material.

12. The method of claim 9 , wherein the third strip portion of the waveguide is doped polycrystalline silicon-germanium material.

13. The method of claim 1 , wherein the first insulating layer and the second insulator layer are thermal oxidation layers.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Monfray Stephane

Classifications

• G02F1/025 Primary

  in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence) · CPC title

• G02F2202/06

  dopant · CPC title

• G02F2202/104

  poly-Si · CPC title

• G02F2202/105

  single crystal Si · CPC title

• G02F2203/50

  Phase-only modulation · CPC title