Read only memory

Patent metadata

Field	Value
Publication number	US-11818883-B2
Application number	US-202117540029-A
Country	US
Kind code	B2
Filing date	Dec 1, 2021
Priority date	Dec 18, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The present description concerns a ROM including at least one first rewritable memory cell.

First claim

What is claimed is:

1. A memory comprising:
memory cells of a first type disposed over a first semiconductor layer of a substrate, the first type being an embedded Select in Trench Memory (eSTM) type memory cell, one of the eSTM type memory cells comprising a select transistor, the select transistor comprising a vertical trench extending to a second semiconductor layer below the first semiconductor layer; and
memory cells of a second type disposed over the first semiconductor layer, each of the memory cells of the second type comprising only one or more transistors, the first type of memory cell being a different type of memory cell than the second type of memory cell.

2. The memory according to claim 1 , wherein, during operation, the memory operates as a read-only memory in which bits of a first state are defined by the memory cells of the first type and bits of a second state are defined by the memory cells of the second type.

3. The memory according to claim 1 , wherein the transistor is a metal-oxide-semiconductor (MOS) transistor.

4. The memory according to claim 3 , wherein the transistor is an N-channel MOS transistor.

5. The memory according to claim 1 , wherein when a threshold voltage of a transistor of the embedded Select in Trench Memory is higher than a reference threshold voltage of the transistor of the memory cells of the second type, then the transistor of the embedded Select in Trench Memory represents a first bit value, and when the threshold voltage of the transistor of the embedded Select in Trench Memory is lower than the reference threshold voltage, then the transistor of the embedded Select in Trench Memory represents a second bit value different from the first bit value.

6. The memory according to claim 1 , wherein the embedded Select in Trench Memory and the transistor comprise a structure successively comprising:
the substrate that is a doped substrate of a first conductivity type;
the second semiconductor layer of a second conductivity type resting on the substrate; and
the first semiconductor layer of a first conductivity type resting on the second semiconductor layer.

7. The memory according to claim 6 , wherein the embedded Select in Trench Memory comprises a first insulated gate and a second insulated gate stacked on each other.

8. The memory according to claim 7 , wherein the first and second insulated gates of the embedded Select in Trench Memory are arranged on a first portion of the surface of the structure.

9. The memory according to claim 7 , wherein the transistor of the memory cells of the second type comprises a third insulated gate having a thickness equal to a sum of the thicknesses of the first and second insulated gates of the first transistor.

10. A read only memory (ROM) comprising:
a plurality of memory cells, each of the plurality of memory cell comprising
a field effect transistor to provide a reference threshold voltage; and
a memory transistor having a first threshold voltage higher than the reference threshold voltage and a second threshold voltage lower than the reference threshold voltage, the memory cell storing a first bit value when the memory transistor has the first threshold voltage and storing a second bit value when the memory transistor has the second threshold voltage.

11. The memory according to claim 10 , wherein the memory transistor is of (embedded Select in Trench Memory) e-STM type, and wherein the field effect transistor is a metal-oxide-semiconductor (MOS) transistor.

12. The memory according to claim 10 , wherein the field effect transistor and the memory transistor comprise a structure successively comprising:
a doped substrate of a first conductivity type;
a first semiconductor layer of a second conductivity type resting on the substrate; and
a second semiconductor layer of a first conductivity type resting on the first semiconductor layer.

13. The memory according to claim 12 , wherein the memory transistor comprises a first insulated gate and a second insulated gate stacked on each other, and wherein the first and second insulated gates of the memory transistor are arranged on a first portion of the surface of the structure.

14. The memory according to claim 13 , wherein the field effect transistor comprises a third insulated gate having a thickness equal to a sum of the thicknesses of the first and second insulated gates of the memory transistor.

15. A method of manufacturing a read only memory (ROM) comprising a plurality of memory cells, each of the plurality of memory cell comprising a first transistor that is rewritable, and a second transistor, the method comprising:
successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer;
forming a cavity at a location of the gate of the transistor of the second transistor in the first gate layer; and
successively depositing a second insulating layer and a second gate layer.

16. The method according to claim 15 , wherein the structure successively comprises:
a second doped substrate of a first conductivity type;
a third semiconductor layer of a second conductivity type resting on the substrate; and
third semiconductor layer of a first conductivity type resting on the first semiconductor layer.

17. The method according to claim 15 , further comprising etching of the first and second insulating layers and of the second gate layer enabling to form an insulated gate of the second transistor.

18. The method according to claim 15 , wherein the first transistor is of e-STM type.

19. The method according to claim 18 , further comprising etching of the first and second insulating layers and of the first and second gate layers to form a stack of two insulated gates of the first transistor.

20. The method according to claim 15 , wherein the semiconductor structure comprises at least one trench made of a semiconductor material and the location of the gate of the transistor of the second transistor is laterally delimited on one side by the at least one trench.

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Rousset

Inventors

• Marzaki Abderrezak
• Lisart Mathieu
• Froment Benoit

Classifications

• H10W42/40

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10B20/367 Primary

  Gate dielectric programmed, e.g. different thickness · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• H01L23/57

  Electricity · mapped topic

• G11C16/0416 Primary

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title