Semiconductor device and method of making a semiconductor device

Patent metadata

Field	Value
Publication number	US-11817486-B2
Application number	US-202218146435-A
Country	US
Kind code	B2
Filing date	Dec 26, 2022
Priority date	May 13, 2021
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an emitter;
a collector;
a base stack located between the emitter and the collector, wherein the base stack comprises an intrinsic base region; and
a base electrode comprising a silicide, wherein the silicide of the base electrode is in direct contact with the base stack, the semiconductor device is provided on a major surface of a semiconductor die, and a plane of contact between the silicide of the base electrode and the intrinsic base region of the base stack is oriented at a non-zero, non-orthogonal angle with respect to the major surface.

2. The semiconductor device of claim 1 , wherein the silicide of the base electrode extends between a part of the emitter and a part of the base stack.

3. The semiconductor device of claim 1 , wherein the collector is located beneath the major surface, wherein the base stack is located above the collector, and wherein the emitter is located above the base stack.

4. The semiconductor device of claim 1 , wherein the base electrode is located on one or more layers of dielectric, to electrically isolate the base electrode from the collector.

5. The semiconductor device of claim 1 , further comprising additional silicide on the emitter, wherein the additional silicide on the emitter is a same type of silicide as the silicide of the base electrode.

6. The semiconductor device of claim 1 , wherein the silicide comprises CoSi 2 , NiSi or NiPtSi.

7. The semiconductor device of claim 1 , wherein the base electrode is in direct contact with the intrinsic base region of the base stack.

8. The semiconductor device of claim 1 , wherein a part of the base electrode in direct contact with the intrinsic base region of the base stack extends laterally beneath a dielectric layer, where the dielectric layer at least partially isolates the base electrode from the emitter.

9. A semiconductor device comprising:
a collector;
a base stack disposed over the collector, wherein the base stack comprises an intrinsic base region;
an emitter, wherein the base stack is disposed between the emitter and the collector; and
a silicide in direct contact with the base stack, wherein at least a portion of the silicide is disposed directly under the emitter, the semiconductor device is provided on a major surface of a semiconductor die, and a plane of contact between the silicide of the base electrode and the intrinsic base region of the base stack is oriented at a non-zero, non-orthogonal angle with respect to the major surface.

10. The semiconductor device of claim 9 , further comprising:
one or more dielectric layers that electrically isolate the silicide from the collector.

11. The semiconductor device of claim 9 , further comprising:
an additional silicide on the emitter, wherein the additional silicide on the emitter is a same type of silicide as the silicide in direct contact with the base stack.

12. The semiconductor device of claim 9 , wherein the silicide comprises material selected from the group consisting of CoSi 2 , NiSi, and NiPtSi.

13. The semiconductor device of claim 9 , wherein the silicide is in direct contact with the intrinsic base region of the base stack.

14. The semiconductor device of claim 9 , wherein at least a portion of the silicide extends laterally beneath a dielectric layer, the portion of the silicide is in direct contact with the base stack, and the dielectric layer at least partially isolates the silicide from the emitter.

15. A heterojunction bipolar transistor comprising:
a collector formed in a semiconductor substrate;
a base stack disposed over and at least partially in contact with the collector, wherein the base stack comprises an intrinsic base region; and
a base electrode comprising a silicide, wherein the silicide of the base electrode is in direct contact with the base stack, the semiconductor device is provided on a major surface of a semiconductor die, and a plane of contact between the silicide of the base electrode and the intrinsic base region of the base stack is oriented at a non-zero, non-orthogonal angle with respect to the major surface.

16. The heterojunction bipolar transistor of claim 15 , wherein the base stack further comprises a first silicon layer disposed under the intrinsic base region and a second silicon layer disposed over the intrinsic base region, and the silicide of the base electrode is in direct contact with the intrinsic base region of the base stack.

17. The heterojunction bipolar transistor of claim 15 , further comprising:
an emitter disposed over the base stack, wherein a location at which the silicide of the base electrode directly contacts the base stack is directly between the emitter and the collector.

Assignees

• Nxp Usa Inc

Inventors

• Kirchgessner James Albert
• John Jay Paul
• Kwan Steven

Classifications

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D10/861

  having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon · CPC title

• H10D10/021

  of heterojunction BJTs [HBT] · CPC title