Thin film transistor and method for manufacturing the same, array substrate, and display device

Patent metadata

Field	Value
Publication number	US-11817460-B2
Application number	US-202017263748-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 27, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a gate;
a gate insulating layer covering the gate;
an active layer disposed on a side of the gate insulating layer away from the gate, the active layer including a polysilicon pattern and an amorphous silicon pattern disposed on at least one side of the polysilicon pattern;
an ionized amorphous silicon layer disposed on a side of the active layer away from the gate, the ionized amorphous silicon layer being in contact with the gate insulating layer;
a source and a drain that are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, the source and the drain being coupled to the active layer through the ionized amorphous silicon layer, and at least one of the source and the drain being coupled to the amorphous silicon pattern; and
a barrier layer disposed on the side of the active layer away from the gate, a material of the barrier layer including silicon dioxide, wherein
an edge of the ionized amorphous silicon layer proximate to the active layer overlaps on a surface of the barrier layer away from the gate;
an orthographic projection of the polysilicon pattern on a surface of the gate away from the gate insulating layer is within a range of an orthographic projection of the barrier layer on the surface of the gate away from the gate insulating layer, and an edge of the orthographic projection of the barrier layer on the surface of the gate away from the gate insulating layer coincides with an edge of an orthographic projection of the active layer on the surface of the gate away from the gate insulating layer;
the ionized amorphous silicon layer includes an ion doped sub-layer and an amorphous silicon sub-layer;
the ion doped sub-layer is farther away from the gate than the amorphous silicon sub-layer; and
a thickness of the amorphous silicon sub-layer is within a range of 500 Å to 1000 Å, and a thickness of the ion doped sub-layer is within a range of 500 Å to 1000 Å.

2. The thin film transistor according to claim 1 , wherein a density of the gate insulating layer is less than a density of the active layer.

3. The thin film transistor according to claim 1 , wherein a material of the gate insulating layer includes silicon oxide.

4. The thin film transistor according to claim 1 , wherein the gate insulating layer includes a first gate insulating sub-layer and a second gate insulating sub-layer that are stacked;
a material of the first gate insulating sub-layer includes silicon dioxide, and a material of the second gate insulating sub-layer includes silicon nitride; and
the first gate insulating sub-layer is closer to the ionized amorphous silicon layer than the second gate insulating sub-layer.

5. The thin film transistor according to claim 4 , wherein a thickness of the first gate insulating sub-layer is within a range of 1000 Å to 2000 Å, and a thickness of the second gate insulating sub-layer is within a range of 2500 Å to 3000 Å.

6. The thin film transistor according to claim 1 , wherein the amorphous silicon pattern surrounds the polysilicon pattern in directions parallel to a surface of the gate away from the gate insulating layer, and the source and the drain are coupled to the amorphous silicon pattern.

7. The thin film transistor according to claim 6 , wherein widths of portions of the amorphous silicon pattern located on two opposite sides of the polysilicon pattern are equal.

8. The thin film transistor according to claim 6 , wherein in a direction parallel to the surface of the gate away from the gate insulating layer and to a connection line between the source and the drain, a width of a portion of the amorphous silicon pattern on a side of the polysilicon pattern is within a range of 2 μm to 5 μm.

9. The thin film transistor according to claim 1 , wherein a thickness of the barrier layer is within a range of 1000 Å to 1500 Å.

10. An array substrate, comprising the thin film transistor according to claim 1 .

11. A display device, comprising the array substrate according to claim 10 .

12. A method for manufacturing a thin film transistor, the method comprising:
forming a gate of the thin film transistor on a substrate;
forming a gate insulating layer covering the gate on a side of the gate away from the substrate;
forming an active layer on a side of the gate insulating layer away from the gate, the active layer including a polysilicon pattern and an amorphous silicon pattern disposed on at least one side of the polysilicon pattern;
forming an ionized amorphous silicon layer on a side of the active layer away from the gate insulating layer, the ionized amorphous silicon layer being in contact with the gate insulating layer;
forming a source and a drain on a side of the ionized amorphous silicon layer away from the gate insulating layer, the source and the drain being coupled to the active layer through the ionized amorphous silicon layer, and at least one of the source and the drain being coupled to the amorphous silicon pattern; and
forming a barrier layer on the side of the active layer away from the gate, a material of the barrier layer including silicon dioxide, wherein
an edge of the ionized amorphous silicon layer proximate to the active layer overlaps on a surface of the barrier layer away from the gate;
an orthographic projection of the polysilicon pattern on a surface of the gate away from the gate insulating layer is within a range of an orthographic projection of the barrier layer on the surface of the gate away from the gate insulating layer, and an edge of the orthographic projection of the barrier layer on the surface of the gate away from the gate insulating layer coincides with an edge of an orthographic projection of the active layer on the surface of the gate away from the gate insulating layer;
the ionized amorphous silicon layer includes an ion doped sub-layer and an amorphous silicon sub-layer;
the ion doped sub-layer is farther away from the gate than the amorphous silicon sub-layer; and
a thickness of the amorphous silicon sub-layer is within a range of 500 Å to 1000 Å, and a thickness of the ion doped sub-layer is within a range of 500 Å to 1000 Å.

13. The method for manufacturing the thin film transistor according to claim 12 , wherein forming the active layer includes:
depositing an amorphous silicon material on the side of the gate insulating layer away from the gate to form a first amorphous silicon film;
using a partial laser annealing process to crystallize the first amorphous silicon film to form the polysilicon pattern;
depositing the material for forming the barrier layer on the crystallized first amorphous silicon film to form a barrier film;
using a first mask to pattern the barrier film and the crystallized first amorphous silicon film; and
removing portions of the barrier film and the crystallized first amorphous silicon film other than regions thereof to be formed into the active layer to form the barrier layer and the amorphous silicon pattern, so as to obtain the active layer including the polysilicon pattern and the amorphous silicon pattern.

14. The method for manufacturing the thin film transistor according to claim 12 , wherein forming the gate insulating layer, the ionized amorphous silicon layer, the source and the drain includes:
depositing a silicon nitride material on a side of the gate away from the substrate to form a second gate insulating sub-layer;
depositing a silicon dioxide material on a side of the second gate insulating sub-layer away from the substrate to form a first gate insulating sub-layer, so as to obtain the gate insulating layer i

Assignees

• Boe Technology Group Co Ltd

Inventors

• Luo Chao
• Guan Feng
• Wang Zhi
• Du Jianhua
• Lv Yang
• Qiang Zhaohui
• Li Chao

Classifications

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/0229

  characterised by control of the annealing or irradiation parameters · CPC title

• H10D30/6746

  Amorphous silicon · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title