Thin Film Transistor and Method of Fabricating the Same, Array Substrate and Method of Fabricating the Same, and Display Device

Patent metadata

Field	Value
Publication number	US-2016254285-A1
Application number	US-201514768009-A
Country	US
Kind code	A1
Filing date	Jan 8, 2015
Priority date	Sep 16, 2014
Publication date	Sep 1, 2016
Grant date	—

Abstract

The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

First claim

1 . A low-temperature polysilicon thin film transistor, comprising a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line, wherein
the gate, the source and the drain are provided in the same layer and comprise the same material; the gate insulation layer is provided on the gate, the active layer is provided on the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other; the passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein; and the first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

2 . The low-temperature polysilicon thin film transistor of claim 1 , wherein the material of the gate, the source and the drain comprises one or more of molybdenum, molybdenum niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper.

3 . The low-temperature polysilicon thin film transistor of claim 1 , wherein the material of the gate insulation layer comprises one or more of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride and aluminum oxide.

4 . A method of fabricating a low-temperature polysilicon thin film transistor, comprising steps of:
forming patterns comprising a gate, a source, a drain, a gate insulation layer and an active layer of the thin film transistor on a substrate by one patterning process, the gate, the source and the drain being provided in the same layer, the gate insulation layer being provided on the gate, the active layer being provided on the gate insulation layer, and the pattern of the gate, the pattern of the gate insulation layer and the pattern of the active layer coinciding with each other; forming a passivation layer on the substrate subjected to above step; and forming a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer in the passivation layer by patterning process, and forming a pattern of a first electrode connection line for connecting the source with the active layer through the first via hole and the third via hole and a pattern of a second electrode connection line for connecting the drain with the active layer through the second via hole and the fourth via hole.

5 . The method of fabricating the low-temperature polysilicon thin film transistor of claim 4 , wherein the step of forming patterns comprising a gate, a source, a drain, a gate insulation layer and an active layer of the thin film transistor on a substrate by one patterning process comprises:
sequentially depositing a metal film, a gate insulation layer film and an active layer film on the substrate, and coating a first photoresist layer on the active layer film; performing exposure and development on the first photoresist layer, so that a thickness of remaining photoresist corresponding to positions of the source and the drain is a first thickness, and a thickness of remaining photoresist corresponding to a position of the gate is a second thickness, the first thickness being smaller than the second thickness; removing exposed active layer film; removing exposed gate insulation layer film; removing exposed metal film; removing the photoresist with the first thickness; removing exposed active layer film; removing exposed gate insulation layer film; and removing remaining photoresist.

6 . The method of fabricating the low-temperature polysilicon thin film transistor of claim 4 , wherein the step of forming the first via hole, the second via hole, the third via hole, the fourth via hole, the first electrode connection line and the second electrode connection line comprises:
coating a second photoresist layer on the substrate on which the passivation layer is formed; performing exposure and development on the second photoresist layer, so that the photoresist corresponding to positions of the first via hole, the second via hole, the third via hole and the fourth via hole are removed, a thickness of remaining photoresist corresponding to positions of the first electrode connection line and the second electrode connection line is a third thickness, and a thickness of remaining photoresist at other regions is a fourth thickness, the third thickness being smaller than the fourth thickness; removing exposed passivation layer to form the first via hole, the second via hole, the third via hole and the fourth via hole; removing the photoresist with the third thickness; forming a conductive film; and removing remaining photoresist by stripping, while removing the conductive film on the photoresist, so as to form the first electrode connection line and the second electrode connection line.

7 . An array substrate, comprising the low-temperature polysilicon thin film transistor of claim 1 .

8 . The array substrate of claim 7 , further comprising a pixel electrode and a pixel defining layer, wherein
the pixel electrode is connected with the second electrode connection line, the pixel electrode, the first electrode connection line and the second electrode connection line are provided in the same layer and comprise the same material; the pixel defining layer is provided above the pixel electrode.

9 . The array substrate of claim 8 , further comprising a plurality of gate lines and a plurality of data lines intersecting with each other and insulated from each other, wherein
each gate line comprises a plurality of gate line strips and a third electrode connection line connecting two adjacent gate line strips in the gate line through fifth via holes penetrating through the passivation layer; the gate line strips, the data lines, the gate, the source and the drain are provided in the same layer and comprise the same material; the material of the third electrode connection line is the same as that of the pixel electrode.

10 . The array substrate of claim 8 , further comprising a plurality of gate lines and a plurality of data lines intersecting with each other and insulated from each other, wherein
each data line comprises a plurality of data line strips and a fourth electrode connection line connecting two adjacent data line strips in the data line through sixth via holes penetrating through the passivation layer; the data line strips, the gate lines, the gate, the source and the drain are provided in the same layer and comprise the same material; the material of the fourth electrode connection line is the same as that of the pixel electrode.

11 . A method of fabricating an array substrate, comprising the method of fabricating the low-temperature polysilicon thin film transistor of claim 4 .

12 . The method of fabricating the array substrate of claim 11 , wherein a pattern of a pixel electrode that is connected with the second electrode connection line is formed while forming the first via hole, the second via hole, the third via hole, the fourth via hole, the first electrode connection line and the second electrode connection line.

13 . The method of fabricating the array substrate of claim 12 , fu

Assignees

• Boe Technology Group Co Ltd
• Boe Tech Co Ltd

Inventors

• Long Chunping
• Wang Zuqiang

Classifications

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0229

  characterised by control of the annealing or irradiation parameters · CPC title

• H10D86/0225

  using crystallisation-promoting species, e.g. using a Ni catalyst · CPC title

• H10D86/0223

  comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials · CPC title