Semiconductor package

Patent metadata

Field	Value
Publication number	US-9570400-B2
Application number	US-201414573134-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	May 2, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor chip;
an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and
a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient, the lower structure including a lower insulating layer under the semiconductor chip and the upper structure, the second thermal expansion coefficient being a thermal expansion coefficient of the lower insulating layer, wherein
the upper structure includes:
a die attach film on an upper surface of the semiconductor chip,
a reinforcing plate attached to the die attach film,
an upper insulating layer on the reinforcing plate,
an upper plug through a hole in the upper insulating layer, the upper plug filling the hole in the upper insulating layer, and
an upper solder resist on the upper insulating layer and that partially exposes the upper plug, and

the first thermal expansion coefficient is an average of thermal expansion coefficients of the die attach film, the upper insulating layer, and the upper solder resist.

2. The semiconductor package as claimed in claim 1 , wherein the semiconductor chip has a thickness of greater than or equal to a thickness of the die attach film.

3. The semiconductor package as claimed in claim 1 , wherein the lower structure includes a conductive pattern in the lower insulating layer and electrically connected to the semiconductor chip, wherein the lower insulating layer is on a lower surface of the upper insulating layer to partially surround the semiconductor chip.

4. The semiconductor package as claimed in claim 3 , wherein the lower structure further includes a lower solder resist on a lower surface of the lower insulating layer and that partially exposes the conductive pattern, and the second thermal expansion coefficient is an average of thermal expansion coefficients of the lower insulating layer and the lower solder resist.

5. The semiconductor package as claimed in claim 3 , wherein the lower structure further includes a dummy core in the lower insulating layer and that surrounds the semiconductor chip.

6. The semiconductor package as claimed in claim 3 , wherein the lower structure further includes a lower plug in the lower insulating layer adjacent to the upper structure and electrically connected to the conductive pattern.

7. The semiconductor package as claimed in claim 1 , wherein the semiconductor chip includes a logic chip.

8. The semiconductor package as claimed in claim 1 , further comprising a memory package stacked on the upper structure.

9. A semiconductor package, comprising:
a semiconductor chip;
a die attach film on an upper surface of the semiconductor chip;
a reinforcing plate attached to the die attach film;
an upper insulating layer on the reinforcing plate;
a lower insulating layer under the semiconductor chip; and
a conductive pattern in the lower insulating layer and electrically connected to the semiconductor chip,
an average of thermal expansion coefficients of the die attach film and the upper insulating layer being greater than or equal to a thermal expansion coefficient of the lower insulating layer, and the reinforcing plate having a thickness greater than a thickness of the conductive pattern.

10. The semiconductor package as claimed in claim 9 , wherein a difference between the average of the thermal expansion coefficients of the die attach film and the upper insulating layer, and the thermal expansion coefficient of the lower insulating layer is greater than or equal to about 30 ppm.

11. The semiconductor package as claimed in claim 9 , further comprising a dummy core in the lower insulating layer and that surrounds the semiconductor chip.

12. The semiconductor package as claimed in claim 11 , further comprising a plug through the upper insulating layer, the dummy core, and the lower insulating layer and electrically connected to the conductive pattern.

13. A semiconductor package, comprising:
a semiconductor chip;
an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient and including:
an upper insulating layer on an upper surface of the semiconductor chip, and
an upper plug through the upper insulating layer; and

a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient, a difference between the first thermal expansion coefficient and the second thermal expansion coefficient being greater than or equal to about 30 ppm, wherein the upper plug includes:
a main contact in a hole of the upper insulating layer;
an upper contact extending from an upper end of the main contact and on an upper surface of the upper insulating layer; and
a lower contact extending from a lower end of the main contact and on a lower surface of the upper insulating layer.

14. The semiconductor package as claimed in claim 13 , wherein the upper structure includes:
a die attach film on an upper surface of the semiconductor chip;
a reinforcing plate attached to the die attach film; and
an upper solder resist on the upper insulating layer and that partially exposes the upper plug,
wherein the upper insulating layer is on the reinforcing plate.

15. The semiconductor package as claimed in claim 14 , wherein the lower structure includes:
a first lower insulating layer;
a second lower insulating layer;
a third lower insulating layer;
a fourth lower insulating layer; and
a lower solder resist on a lower surface of the lower insulating layer and that partially exposes the conductive pattern.

16. The semiconductor package as claimed in claim 15 , wherein:
the first thermal expansion coefficient is an average of thermal expansions of the upper solder resist, the upper insulating layer, and the die attach film; and
the second thermal expansion coefficient is an average of thermal expansions of the first lower insulating layer, the second lower insulating layer, the third lower insulating layer, the fourth lower insulating layer, and the lower solder resist.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Bo-Na
• Lee Seok-Won
• Cho Eun-Seok
• Kim Dong-Han
• Choi Kyoung-Sei
• Kang Sa-Yoon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title