Semiconductor device comprising a can housing a semiconductor die which is embedded by an encapsulant

Patent metadata

Field	Value
Publication number	US-11817418-B2
Application number	US-202017103511-A
Country	US
Kind code	B2
Filing date	Nov 24, 2020
Priority date	Nov 25, 2019
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A semiconductor device includes a conductive can include a flat portion and at least one peripheral rim portion extending from an edge of the flat portion, a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can, an electrical interconnector connected with the second contact pad, and an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant.

First claim

The invention claimed is:

1. A semiconductor device, comprising
a conductive can comprising a flat portion and at least one peripheral rim portion extending from an edge of the flat portion;
a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the conductive can;
an electrical interconnector connected with the second contact pad; and
an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, the encapsulant also filling a space between the conductive can and the side faces of the semiconductor die,
wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant,
wherein the electrical interconnector comprises a region of solder material that is directly in contact with the second contact pad,
wherein the encapsulant is disposed exclusively on a same side of the conductive can as the semiconductor die.

2. The semiconductor device according to claim 1 , wherein
a top surface of the can is exposed by or not covered by the encapsulant.

3. The semiconductor device according to claim 1 , wherein
a height of the electrical interconnector is in a range of 40% to 80% of a height of the encapsulant, wherein the height is measured from the second main face of the semiconductor die.

4. The semiconductor device according to claim 1 , wherein
the encapsulant comprises one or more of an organic epoxy compound, an epoxy resin, and a biphenyl epoxy resin.

5. The semiconductor device according to claim 1 , wherein the encapsulant comprises a filler material, wherein the filler material comprises particles of silica.

6. The semiconductor device according to claim 1 , wherein no solder is provided on the external surface of the electrical interconnector.

7. The semiconductor device according to claim 1 , wherein the semiconductor die comprises a power semiconductor die comprising terminals, wherein the rim portion is connected with one terminal, and the one or more electrical interconnectors are connected with the other terminals.

8. The semiconductor device according to claim 1 , wherein an entire height of the encapsulant is greater than a height of the cavity.

9. A semiconductor device, comprising
a conductive can comprising a flat portion and at least one peripheral rim portion extending from an edge of the flat portion;
a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the conductive can;
an electrical interconnector connected with the second contact pad;
an encapsulant disposed only under the semiconductor die so as to surround the electrical interconnector;
an external surface of the electrical interconnector is recessed from an external surface of the encapsulant; and
a PCB having solder pads at an upper surface thereof, the solder pads in contact with the at least one peripheral rim portion and the electrical interconnector,
wherein the encapsulant does not fill a space between the conductive can and the side faces of the semiconductor die,
wherein the encapsulant is in contact with an upper surface of the PCB.

10. The semiconductor device according to claim 9 , wherein
a top surface of the can is exposed by or not covered by the encapsulant.

11. The semiconductor device according to claim 9 , wherein
a height of the electrical interconnector is in a range of 40% to 80% of a height of the encapsulant, wherein the height is measured from the second main face of the semiconductor die.

12. The semiconductor device according to claim 9 , wherein
the encapsulant comprises one or more of an organic epoxy compound, an epoxy resin, and a biphenyl epoxy resin.

13. The semiconductor device according to claim 9 , wherein the encapsulant comprises a filler material, wherein the filler material comprises particles of silica.

14. The semiconductor device according to claim 9 , wherein the electrical interconnector comprises one or more of a solder based alloy, an alloy of Sn/Ag/Cu, and a copper pillar.

15. The semiconductor device according to claim 9 , wherein no solder is provided on the external surface of the electrical interconnector.

16. The semiconductor device according to claim 9 , wherein the semiconductor die comprises a power semiconductor die comprising terminals, wherein the rim portion is connected with one terminal, and the one or more electrical interconnectors are connected with the other terminals.

Assignees

• Infineon Technologies Ag

Inventors

• Lim Wei Lee
• Toh Run Hong
• Yeap Peng Liang

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07355

  changes in materials · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/01351

  Changing the shapes of die-attach connectors · CPC title