Molded semiconductor package with high voltage isolation

Patent metadata

Field	Value
Publication number	US-11817407-B2
Application number	US-202217746306-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	Dec 7, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.

First claim

What is claimed is:

1. A molded semiconductor package, comprising:
a first semiconductor die attached to a first substrate, the first semiconductor die comprising a first bond pad at a first side of the first semiconductor die which faces away from the first substrate and an insulating layer covering the first side;
an electrical conductor attached to a part of the first bond pad exposed by an opening in the insulating layer;
a mold compound encasing the first semiconductor die; and
an electrically insulative material filling the opening in the insulating layer and sealing the part of the first bond pad exposed by the opening in the insulating layer,
wherein the electrically insulative material separates the mold compound from the part of the first bond pad exposed by the opening in the insulating layer.

2. The molded semiconductor package of claim 1 , wherein the first bond pad is galvanically isolated from circuitry included in the first semiconductor die such that no direct conduction path is provided between the first bond pad and the circuitry.

3. The molded semiconductor package of claim 2 , wherein the first semiconductor die further comprises a coreless transformer configured to electromagnetically couple the first bond pad to the circuitry.

4. The molded semiconductor package of claim 3 , wherein the circuitry comprises a high side driver and a low side driver for a half-bridge.

5. The molded semiconductor package of claim 1 , wherein the electrically insulative material and the insulating layer are cross-linked to one another along an interface between the electrically insulative material and the insulating layer.

6. The molded semiconductor package of claim 5 , wherein the electrically insulative material comprises polyimide, wherein the insulating layer comprises imide, and wherein the polyimide is cross-linked with the imide along the interface between the electrically insulative material and the insulating layer.

7. The molded semiconductor package of claim 1 , wherein a breakdown voltage of the electrically insulative material is 400 V/μm or higher.

8. The molded semiconductor package of claim 1 , wherein the electrical conductor is a wire bond, wherein a ball end of the wire bond is attached to the part of the first bond pad exposed by the opening in the insulating layer, and wherein the electrically insulative material covers a lower part of the ball end disposed closest to the first bond pad such that the lower part of the ball end is separated from the mold compound by the electrically insulative material.

9. The molded semiconductor package of claim 8 , wherein the electrically insulative material covers the entire ball end of the wire bond such that the entire ball end of the wire bond is separated from the mold compound by the electrically insulative material.

10. The molded semiconductor package of claim 1 , wherein the electrically insulative material and the insulating layer each have a microroughened surface which increases adhesion by the mold compound.

11. The molded semiconductor package of claim 1 , wherein the entire side of the first semiconductor die which faces away from the first substrate is covered by the electrically insulative material.

12. The molded semiconductor package of claim 1 , further comprising a second semiconductor die attached to a second substrate, wherein the mold compound encases the second semiconductor die, and wherein the electrical conductor is attached at a first end to the part of the first bond pad of the first semiconductor die exposed by the opening in the insulating layer and at a second end to a first bond pad of the second semiconductor die.

13. The molded semiconductor package of claim 1 , wherein the first semiconductor die comprises a plurality of bond pads at the first side of the first semiconductor die, wherein each bond pad is exposed by an opening in the insulating layer, wherein the electrically insulative material fills each opening in the insulating layer and seals the part of each bond pad exposed by the corresponding opening in the insulating layer, and wherein the electrically insulative material separates the mold compound from the part of each bond pad exposed by the corresponding opening in the insulating layer.

14. The molded semiconductor package of claim 13 , wherein the electrically insulative material is a single uninterrupted layer.

15. A method of producing a molded semiconductor package, the method comprising:
attaching a first semiconductor die to a first substrate, the first semiconductor die comprising a first bond pad at a first side of the first semiconductor die which faces away from the first substrate and an insulating layer covering the first side;
attaching an electrical conductor to a part of the first bond pad exposed by an opening in the insulating layer;
encasing the first semiconductor die in a mold compound; and
filling the opening in the insulating layer and sealing the part of the first bond pad exposed by the opening in the insulating layer with an electrically insulative material,
wherein the electrically insulative material separates the mold compound from the part of the first bond pad exposed by the opening in the insulating layer.

16. The method of claim 15 , wherein filling the opening in the insulating layer with the electrically insulative material comprises:
dispensing a material that comprises a polyimide resin into the opening in the insulating layer; and
curing the polyimide resin.

17. The method of claim 16 , wherein the insulating layer comprises imide, and wherein the polyimide resin is cross-linked with the imide after the curing.

18. The method of claim 15 , wherein attaching the electrical conductor comprises:
attaching a ball end of a wire bond to the part of the first bond pad exposed by the opening in the insulating layer,
wherein after filling the opening in the insulating layer with the electrically insulative material, the electrically insulative material covers a lower part of the ball end disposed closest to the first bond pad such that the lower part of the ball end is separated from the mold compound by the electrically insulative material.

19. The method of claim 18 , wherein after filling the opening in the insulating layer with the electrically insulative material, the electrically insulative material covers the entire ball end of the wire bond such that the entire ball end of the wire bond is separated from the mold compound by the electrically insulative material.

20. The method of claim 15 , wherein filling the opening in the insulating layer with the electrically insulative material comprises:
covering the entire side of the first semiconductor die which faces away from the first substrate with the electrically insulative material.

21. The method of claim 20 , further comprising:
before encasing the first semiconductor die in the mold compound, applying an adhesion promoter that comprises zinc and chromium to an exposed surface of the electrically insulative material and the insulating layer.

Assignees

• Infineon Technologies Ag

Inventors

• Wan Shao Ping
• Acquitan Eric Brion
• Reynoso Dexter
• SCHREDL JüRGEN
• Yong Woon Yik

Classifications

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W74/016

  using moulds · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/534

  being rectangular · CPC title