Semiconductor device and control method

Patent metadata

Field	Value
Publication number	US-11816235-B2
Application number	US-201916573407-A
Country	US
Kind code	B2
Filing date	Sep 17, 2019
Priority date	Oct 15, 2018
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The semiconductor device includes a control unit having redundant processors, a memory storing target data, a secure memory storing a key used for encryption or decryption processing, an cryptographic unit, a secure processor instructing cryptographic processing to the cryptographic unit in response to a request from the control unit, a first bus coupled to the control unit, the memory, the cryptographic unit, and the secure processor, and a second bus coupled to the secure memory, the cryptographic unit, and the secure processor. The control unit communicates with the memory via a predetermined error detection mechanism, the cryptographic unit includes a plurality of cryptographic processors that independently perform cryptographic processing on target data using a key based on an instruction, and each of the plurality of cryptographic processors includes a data transfer unit that performs data transfer with the memory via the error detection mechanism.

First claim

What is claimed is:

1. A semiconductor device comprising:
a controller that 1) generates a cryptographic request with request information including an address of target data and 2) includes a master processor and a checker processor that execute a same process as one another in a lock step, a result of the checker processor being compared with a result of the master processor;
a memory that stores the request information;
a secure memory that stores a key used for encryption or decryption;
a secure processor that generates a cryptographic instruction with setting information including an address extracted from the request information in response to the cryptographic request from the controller;
a cryptographic unit including a master cryptographic processor and a checker cryptographic processor that perform a same cryptographic process as one another, using the key, on data stored in the extracted address of the memory based on the setting information, a processing result of the checker cryptographic processor being compared with a processing result of the master cryptographic processor;
a first bus coupled to the controller, the memory, the cryptographic unit, and the secure processor; and
a second bus coupled to the secure memory, the cryptographic unit, and the secure processor,
wherein the controller communicates with the memory via a predetermined error detection mechanism,
wherein each of the master cryptographic processor and the checker cryptographic processor includes a data transfer unit that performs a data transfer with the memory via the error detection mechanism, and
wherein the controller detects a failure of the secure processor by comparing the address of target data included in the request information stored in the memory with the address included in the setting information after the cryptographic process.

2. The semiconductor device according to claim 1 , wherein the master cryptographic processor stores the processing result of the master cryptographic processor in the memory using the data transfer unit, and the checker cryptographic processor discards the processing result of the checker cryptographic processor.

3. The semiconductor device according to claim 1 , wherein each of the master cryptographic processor and the checker cryptographic processor performs, as the cryptographic process, encryption for the data and generation of a message authenticating code using the key when the data is data to be transmitted to another semiconductor device.

4. The semiconductor device according to claim 1 , wherein each of the master cryptographic processor and the checker cryptographic processor decrypts the data and generates a first message authenticating code as the cryptographic process when the data is received data from another semiconductor device.

5. The semiconductor device according to claim 4 ,
wherein the received data includes encrypted data using the key and a second message authentication code generated by the other semiconductor device,
wherein at least the master cryptographic processor stores the decrypted data and the first message authentication code in the memory using the data transferring unit, and
wherein the controller compares the first message authentication code and the second message authentication code stored in the memory to detect a failure of the master cryptographic processor.

6. The semiconductor device according to claim 4 ,
wherein the received data includes encrypted data using the key and a second message authentication code generated by the other semiconductor device, and
wherein at least the master cryptographic processor further comprises a comparator that compares the second message authentication code obtained from the memory using the data transfer unit with the first message authentication code.

7. The semiconductor device according to claim 6 , wherein the master cryptographic processor stores the decrypted data and the comparison result by the comparator in the memory using the data transferring unit, and the controller discards the decrypted data when the comparison result stored in the memory indicates a mismatch.

8. The semiconductor device according to claim 1 ,
wherein the request information further includes a type of cryptographic algorithm,
wherein the setting information further includes the type of cryptographic algorithm extracted from the request information, and
wherein the master processor and the checker cryptographic processor perform the same cryptographic process corresponding to the extracted type of cryptographic algorithm, and
wherein the controller detects a failure of the secure processor by comparing the address of target data included in the request information with the address included in the setting information and by comparing the type of cryptographic algorithm included in the request information with the type of cryptographic algorithm included in the setting information.

9. The semiconductor device according to claim 1 ,
wherein the first bus and the second bus are independent of each other, and
wherein the controller is inaccessible to the second bus.

Assignees

• Renesas Electronics Corp

Inventors

• Ito Kenichi
• Yamate Akihiro
• Hosotani Akira

Classifications

• G06F21/6209 Primary

  to a single file or object, e.g. in a secure envelope, encrypted and accessed using a key, or with access control rules appended to the object itself · CPC title

• G06F21/64

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title