Dual lock step processor system

Patent metadata

Field	Value
Publication number	US-11200312-B1
Application number	US-201816025731-A
Country	US
Kind code	B1
Filing date	Jul 2, 2018
Priority date	Jul 2, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A dual lock step processor system includes a first processor connected to a first memory, a second processor connected to a second memory, compiler engine, a first instruction engine operably connected to a first memory, and a second instruction engine operably connected to a second memory. The first instruction engine is configured to store a program value; encode the first program value using a first differential encoding and the compiler engine to generate a first encoded program value; and write the first encoded program value into a first address location of a plurality of first address locations. The second instruction engine is configured to store a program value; to encode the first program value using a second differential encoding and the compiler engine to generate a second encoded program value and write the second encoded program value into a second address location of a plurality of second address locations corresponding to the first selected address location.

First claim

What is claimed is:

1. A dual lock step processor system, comprising:
a first processor operably connected to a first memory, the first memory comprising a plurality of first address locations;
the first processor configured to:
receive, from the first memory, a first instruction to store a first program value;
differentially encode the first program value using a first differential encoding to generate a first differentially encoded program value; and
write the first differentially encoded program value into a first selected address location of the plurality of first address locations; and

a second processor operably connected to a second memory, the second memory comprising a plurality of second address locations, each second address location of the plurality of second address locations corresponding to an identical first address location of the plurality of first address locations;
the second processor configured to:
receive, from the second memory, a second instruction to store the first program value;
differentially encode the first program value using a second differential encoding to generate a second differentially encoded program value; and
write the second differentially encoded program value into a second selected address location of the plurality of second address locations corresponding to the first selected address location;

wherein the first processor is further configured to:
receive, from the second memory and subsequent to writing the first differentially encoded program value into the first selected address location, a third instruction to retrieve a first stored value stored in the first selected address location;
retrieve the first stored value from the first selected address location; and
differentially decode the first stored value using the first differential encoding to generate a first differentially decoded stored value; and

wherein the second processor is further configured to:
receive, from the second memory and subsequent to writing the second differentially encoded program value into the second selected address location, a fourth instruction to retrieve a second stored value stored in the second selected address location; and
differentially decode the second stored value using the second differential encoding to generate a second differentially decoded stored value; and

an exploit monitor operably connected to the first processor and the second processor, the exploit monitor configured to:
compare the first differentially decoded stored value to the second differentially decoded stored value; and
responsive to the first differentially decoded stored value being different from the second differentially decoded stored value, interrupt operation of the first processor by generating a first interrupt signal to the first processor, and interrupt operation of the second processor by generating a second interrupt signal to the second processor,
wherein the first differential encoding is a summation encoding to generate the first differentially encoded program value and a subtraction decoding to generate the first differentially decoded stored value,
wherein the summation encoding is a sum of the first program value and the first selected address location, and the subtraction decoding is a subtraction of the first program value and the first selected address location,
wherein the second differential encoding is a subtraction encoding to generate the second differentially encoded program value and a summation decoding to generate the second differentially decoded stored value,
wherein the subtraction encoding is a subtraction of the first program value and the second selected address location, and the summation decoding is a summation of the first program value and the second selected address location.

2. The dual lock step processor system of claim 1 , wherein the exploit monitor is further configured to allow operation of the first processor or the second processor responsive to the first differentially decoded stored value being equal to the second differentially decoded stored value, wherein allowing the operation includes:
the first processor receiving from the first memory, a third instruction to store a second program value; and
the second processor receiving from the second memory, a fourth instruction to store the second program value.

3. The dual lock step processor system of claim 1 , wherein prior to receiving the first instruction by the first processor and second instruction by the second processor, the dual lock step processor system receives a single input, the single input associated with the first instruction and the second instruction.

4. The dual lock step processor system of claim 1 , wherein first processor is further configured to:
receive, from the first memory, a fifth instruction to store a second program value; and
write the second program value into a third selected address location of the plurality of first address locations; and
wherein second processor is further configured to:
receive, from the second memory, a sixth instruction to store the second program value; and
write the second program value into a fourth selected address location of the plurality of second address locations.

5. The dual lock step processor system of claim 4 , wherein the exploit monitor is further configured to interrupt operation the first processor and the second processor responsive to the fifth instruction received by the first processor being different from the sixth instruction received by the second processor.

6. The dual lock step processor system of claim 1 , wherein the first differential encoding is associated with the first selected address location and the second differential encoding is asymmetrically associated with the first selected address location.

7. The dual lock step processor system of claim 1 , wherein the plurality of first address locations is on a first stack of the first memory and wherein the plurality of second address locations is on a second stack of the second memory.

8. A method, comprising:
receiving an input associated with a first program value;
receiving a first instruction to store the first program value;
differentially encoding the first program value using a first differential encoding to generate a first differentially encoded program value on a first processor;
writing the first differentially encoded program value into a first selected address location, the first selected address location being one of a plurality of first address locations of a first memory, the first processor operably connected to the first memory;
receiving a second instruction to store the first program value;
differentially encoding the first program value using a second differential encoding to generate a second differentially encoded program value on a second processor; and
writing the second differentially encoded program value into a second selected address location, the second selected address location being one of a plurality of second address locations of a second memory, wherein the second selected address location in the plurality of second address locations corresponds to an analogous location of the first selected address location in the plurality of first address locations, and wherein the second processor is operably connected to the second memory,
receiving, from the first memory and subsequent to writing the first differentially encoded program value into the first selected address location, a third instruction to retrieve a first stored value stored in the first selected address location;
retrieving the first stored value from the first selected address location;
differentially decoding the first stored value using the first differential encodin

Assignees

• Rockwell Collins Inc

Inventors

• Greve David A
• Potts James N

Classifications

• G06F8/443

  Optimisation · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title