High performance interconnect
US-2018253398-A1 · Sep 6, 2018 · US
US11816052B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11816052-B2 |
| Application number | US-201916659660-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 22, 2019 |
| Priority date | Oct 22, 2019 |
| Publication date | Nov 14, 2023 |
| Grant date | Nov 14, 2023 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: an endpoint circuit to perform an endpoint operation on behalf of a host processor, the endpoint circuit comprising a memory device of a first media type, wherein the memory device is part of a memory expander; and an input/output (I/O) circuit coupled to the endpoint circuit, the I/O circuit including an interface circuit to receive telemetry information comprising bandwidth information of the endpoint circuit, encode the telemetry information into a virtual bus encoding having a value based on the bandwidth information and place the virtual bus encoding into a payload field of a control message, wherein the I/O circuit is to communicate the control message having the payload field including the virtual bus encoding to an upstream device. 2. The apparatus of claim 1 , wherein the memory expander further comprises at least one other memory device of a second media type, the at least one other memory device of the second media type to encode second telemetry information into a second virtual bus encoding and place the second virtual bus encoding into a different portion of the payload field of the control message. 3. The apparatus of claim 1 , wherein the interface circuit is to encode the telemetry information into the virtual bus encoding having a first value when the bandwidth information is less than a first threshold. 4. The apparatus of claim 3 , wherein the interface circuit is to encode the telemetry information into the virtual bus encoding having a second value when the bandwidth information is greater than the first threshold. 5. The apparatus of claim 1 , wherein the interface circuit comprises an encoder to encode the telemetry information into the virtual bus encoding. 6. The apparatus of claim 1 , wherein the I/O circuit is to receive a second control message from the upstream device, the second control message having a second virtual bus encoding, and wherein the interface circuit is to decode the second virtual bus encoding and provide a decoded control message to the endpoint circuit to cause the endpoint circuit to perform at least one operation. 7. The apparatus of claim 1 , wherein the I/O circuit is to asynchronously communicate the control message in response to a logical state change of the endpoint circuit. 8. The apparatus of claim 1 , wherein the control message comprises a control flit of a communication protocol. 9. The apparatus of claim 8 , wherein the control flit comprises a link layer control flit. 10. At least one non-transitory computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising: receiving, in a fabric switch, a plurality of control messages, each of the plurality of control messages received from a downstream device coupled to the fabric switch; extracting an encoding from each of the plurality of control messages, the encoding associated with telemetry information of the corresponding downstream device; selecting the encoding having a highest value of the encoding; and in response to determining that the selected encoding is different than a prior encoding sent to an upstream device coupled to the fabric switch, sending the selected encoding to the upstream device. 11. The at least one non-transitory computer readable storage medium of claim 10 , wherein the method further comprises preventing sending the selected encoding when the selected encoding is not different than a stored encoding stored in a storage of the fabric switch, the stored encoding comprising the prior encoding. 12. The at least one non-transitory computer readable storage medium of claim 11 , wherein the method further comprises storing the selected encoding in the storage when the selected encoding is different than the stored encoding. 13. The at least one non-transitory computer readable storage medium of claim 10 , wherein the method further comprises sending the selected encoding to the upstream device within a control message of a communication protocol. 14. The at least one non-transitory computer readable storage medium of claim 10 , wherein the method further comprises sending a plurality of encodings to the upstream device within the control message, each of the plurality of encodings associated with a different type of downstream device. 15. A system comprising: a host processor having a plurality of cores and a downstream port, at least one of the plurality of cores comprising a rate limiter to control a source of memory traffic based at least in part on a virtual bus encoding received in the downstream port; a fabric switch coupled to the downstream port of the host processor via a first interconnect, the fabric switch including an aggregation circuit, wherein the aggregation circuit is to: receive a plurality of control messages from at least some of a plurality of endpoint devices coupled to the fabric switch; extract a virtual bus encoding from each of the plurality of control messages, the virtual bus encoding associated with telemetry information of the corresponding endpoint device; select the virtual bus encoding having a highest value; and send the virtual bus encoding having the highest value to the host processor; and the plurality of endpoint devices coupled to the fabric switch, wherein the at least some of the plurality of endpoint devices comprise: an input/output (I/O) circuit to receive telemetry information regarding the endpoint device, encode the telemetry information into the virtual bus encoding and send the control message including the virtual bus encoding to the fabric switch. 16. The system of claim 15 , wherein the telemetry information comprises bandwidth information of a memory device of a first media type, wherein the memory device is part of a memory expander. 17. The system of claim 16 , wherein the memory expander further comprises at least one other memory device of a second media type, the at least one other memory device of the second media type to encode second telemetry information into a second virtual bus encoding, and wherein the rate limiter is to not throttle a first source of memory traffic directed to the first media type and throttle a second source of memory traffic directed to the second media type based at least in part on the second virtual bus encoding. 18. The system of claim 16 , wherein the I/O circuit is to encode the telemetry information comprising bandwidth information into the virtual bus encoding having a first value when the bandwidth information is less than a first threshold and encode the telemetry information into the virtual bus encoding having a second value when the bandwidth information is greater than the first threshold. 19. The system of claim 16 , wherein the at least some of the plurality of endpoint devices are to send the plurality of control messages asynchronously and the aggregation circuit is to send the virtual bus encoding having the highest value to the host processor only when there is a change to the highest value.
using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title
for access to input/output bus · CPC title
Hypervisor-specific management and integration aspects · CPC title
on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title
Distribute and route fabrics, e.g. Batcher-Banyan · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.