Front-end circuitry for a data receiver and related systems, methods, and devices

Patent metadata

Field	Value
Publication number	US-11811568-B2
Application number	US-202217818224-A
Country	US
Kind code	B2
Filing date	Aug 8, 2022
Priority date	May 19, 2020
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a first signal path between a signal input terminal and a first equalizer output terminal, the first signal path having a first frequency response responsive to an input signal provided to the signal input terminal; and
a second signal path between the signal input terminal and a second equalizer output terminal, the second signal path having a second frequency response responsive to the input signal provided to the signal input terminal, the second frequency response exhibiting substantially inverse behavior to that of the first frequency response.

2. The apparatus of claim 1 , wherein a second impedance of the second signal path is substantially a square of a reference impedance divided by a first impedance of the first signal path.

3. The apparatus of claim 1 , comprising an amplifier circuit including:
a first amplifier electrically connected to the first equalizer output terminal; and
a second amplifier electrically connected to the second equalizer output terminal.

4. The apparatus of claim 3 , comprising a summing circuit electrically connected to output terminals of the first amplifier and the second amplifier.

5. The apparatus of claim 3 , wherein a gain of the second amplifier is selected as a function of a gain of the fist amplifier.

6. The apparatus of claim 3 , wherein a gain of the second amplifier is one minus a gain of the first amplifier.

7. The apparatus of claim 3 , comprising control circuitry to control a gain of the first amplifier and a gain of the second amplifier.

8. The apparatus of claim 3 , wherein the first amplifier and the second amplifier are programmable-gain amplifiers.

9. The apparatus of claim 3 , comprising:
a first impedance matching network between the first equalizer output terminal and the first amplifier; and
a second impedance matching network between the second equalizer output terminal and the second amplifier.

10. The apparatus of claim 1 , wherein a first impedance of the first signal path and a second impedance of the second signal path are second order impedance networks.

11. The apparatus of claim 1 , comprising a bridge impedance bridging the first signal path to the second signal path.

12. The apparatus of claim 1 , wherein the first signal path and the second signal path are free of a bridge impedance to bridge the first signal path to the second signal path.

13. A method of equalizing an input signal, the method comprising:
generating a first equalizer output signal responsive to the input signal applied to a first signal path, the first signal path having a first impedance; and
generating a second equalizer output signal responsive to the input signal applied to a second signal path, the second signal path having a second impedance, the second impedance substantially a square of a reference impedance divided by the first impedance.

14. The method of claim 13 , comprising:
amplifying the first output signal with a first gain to generate a first amplified signal; and
amplifying the second output signal with a second gain to generate a second amplified signal.

15. The method of claim 14 , comprising summing the first amplified signal with the second amplified signal to generate an equalized output signal.

16. The method of claim 15 , wherein a frequency of the equalized output signal is greater than or equal to ten gigahertz (10 GHz).

17. The method of claim 15 , wherein a frequency of the equalized output signal is substantially 12.8 gigahertz (GHz).

18. An apparatus, comprising:
a first signal path between a signal input terminal and a first equalizer output terminal, the first signal path having a first frequency response responsive to an input signal provided to the signal input terminal;
a second signal path between the signal input terminal and a second equalizer output terminal, the second signal path having a second frequency response responsive to the input signal provided to the signal input terminal, the second frequency response exhibiting substantially inverse behavior to that of the first frequency response over a predetermined passband, and
a variable-gain amplifier to sum amplified versions of a first equalizer output signal from the first equalizer output terminal and a second equalizer output signal from the second equalizer output terminal to generate an equalized output signal.

19. The apparatus of claim 18 , wherein a frequency response of the equalized output signal is substantially flat through the predetermined passband.

20. The apparatus of claim 19 , wherein the predetermined passband extends at least to ten gigahertz (10 GHz).

Assignees

• Microchip Tech Inc
• Microchip Tech Inc

Inventors

• Ransijn Johannes G

Classifications

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H04B1/16

  Circuits · CPC title

• H04B3/14

  characterised by the equalising network used · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/08

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title