Top electrode interconnect structures

Patent metadata

Field	Value
Publication number	US-11810853-B2
Application number	US-202217702255-A
Country	US
Kind code	B2
Filing date	Mar 23, 2022
Priority date	Nov 21, 2018
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.

First claim

What is claimed:

1. A method comprising:
forming a vertical pillar comprising a bottom electrode, one or more switching material, a top electrode and a masking material on the top electrode and further includes a via interconnection;
forming a spacer completely surrounding the via interconnection;
forming an interlevel dielectric material over the vertical pillar;
opening the interlevel dielectric material to expose the masking material;
selectively removing the masking material over the top electrode to form a self-aligned via interconnect;
forming an interconnection by deposited conductive material in the self-aligned via interconnect, which contacts the top electrode;
forming a metallization on the conductive material;
forming a diffusion barrier material directly contacting a top surface of a first metallization feature and directly contacting sidewalls of the bottom electrode; and
forming dielectric material surrounding and directly contacting an outer sidewall surface of the spacer and sidewalls of each of the vertical pillar and a top surface of the diffusion barrier material.

2. The method of claim 1 , wherein the hardmask material are carbon-based organics, oxides, nitrides, amorphous or poly-Si, or combinations thereof.

3. The method of claim 1 , further comprising at least one of a spacer and liner on the masking material, prior to removal and, upon removal, the at least one spacer and the liner defines the self-aligned via interconnect.

4. The method of claim 1 , wherein the spacer completely surrounds the via interconnection, the one or more switching material below the top electrode and devoid of the spacer, and the bottom electrode between a bottom surface of the one or more switching material and a top surface of the first metallization feature and being devoid of the spacer.

5. The method of claim 4 , wherein:
an outer sidewall surface of the spacer and an edge of the top electrode have coplanar sidewalls,
the spacer extends only within a space defined by the top electrode and a bottom surface of a second metallization layer, and
the diffusion barrier material is a different material than the dielectric material.

6. The method of claim 4 , further comprising forming a lower metallization feature and an upper metallization feature connected together by an interconnect structure devoid of any intervening materials.

7. The method of claim 4 , wherein the bottom electrode, the one or more switching materials, the top electrode and the spacer material surrounding the via interconnection have vertically aligned sidewalls forming the vertical pillar.

8. A method, comprising:
forming a lower metallization feature;
forming an upper metallization feature;
forming a bottom electrode in direct contact with the lower metallization feature;
forming one or more switching materials over the bottom electrode;
forming a top electrode over the one or more switching materials;
forming a via interconnection in contact with the top electrode and the upper metallization feature;
forming a spacer material only contacting and surrounding a sidewall of the via interconnection, and contacting a top surface of the top electrode and a bottom surface of the upper metallization feature;
forming dielectric material surrounding and contacting an outer sidewall surface of the spacer material and directly contacting sidewalls of each of the one or more switching materials; and
forming a diffusion barrier material contacting directly with a top surface of the lower metallization feature and sidewalls of the bottom electrode, the diffusion barrier material being different material than the dielectric material,
wherein sidewalls of each of the bottom electrode, the one or more switching materials, the top electrode and an outer surface of the spacer material are coplanar with one another, and with the via interconnection form a vertical pillar structure and the dielectric material directly contacting the sidewalls of the bottom electrode, the sidewalls of the top electrode and an entire top surface of the diffusion barrier material.

9. The method of claim 8 , wherein the via interconnection is a self-aligned via interconnection, the top electrode is in direct contact with the one or more switching materials.

10. The method of claim 8 , wherein the lower metallization feature and the upper metallization feature are connected together by an interconnect structure devoid of any intervening materials.

11. A method, comprising:
forming a first metallization layer;
forming a second metallization layer;
forming a vertical pillar connecting the first metallization layer to the second metallization layer, the vertical pillar including an aligned via interconnection and a spacer completely surrounding the aligned via interconnection and both being in direct contact with a top electrode of the vertical pillar and a bottom surface of the second metallization layer, the vertical pillar further comprising a switching material below the top electrode and which is devoid of the spacer, and a bottom electrode between a bottom surface of the switching material and a top surface of the first metallization feature and which is also devoid of the spacer;
forming the lower metallization feature and the upper metallization feature connected together by an interconnect structure devoid of the aligned via interconnection and the vertical pillar;
forming a diffusion barrier material directly contacting a top surface of the first metallization layer and directly contacting sidewalls of the bottom electrode;
forming dielectric material surrounding and directly contacting an outer sidewall surface of the spacer and sidewalls of each of the vertical pillar and a top surface of the diffusion barrier material,
wherein an outer sidewall surface of the spacer and an edge of the top electrode have coplanar sidewalls,
wherein the spacer extends only within a space defined by the top electrode of the vertical pillar and the bottom surface of the second metallization layer, and
wherein the diffusion barrier material is a different material than the dielectric material.

12. The method of claim 11 , wherein the self-aligned via interconnection is in a via which exposes the top electrode and further comprising a sidewall structure contacting the spacer, a sidewall of the vertical pillar and the diffusion barrier material.

13. The method of claim 12 , wherein the spacer defines the self-forming self-aligned via and completely surrounds and is in direct contact with the self-aligned via interconnection and a sidewall structure, and the sidewall structure being in direct contact with an outer surface of the vertical pillar.

14. The method of claim 13 , wherein the vertical pillar has a narrower cross-section at the self-forming self-aligned via compared to the top electrode.

Assignees

• Globalfoundries Us Inc

Inventors

• Kim Il Goo
• Augur Roderick A

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title