Process manufacturing method, method for adjusting threshold voltage device, and storage medium

Patent metadata

Field	Value
Publication number	US-11809802-B2
Application number	US-202117198462-A
Country	US
Kind code	B2
Filing date	Mar 11, 2021
Priority date	Mar 31, 2020
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided. One form of a process manufacturing method includes: determining a type of to-be-formed MOS device and a corresponding threshold voltage interval; obtaining, according to a MOS device type and the corresponding threshold voltage interval, a corresponding threshold voltage adjustment process by querying a pre-configured first mapping relationship of the threshold voltage interval and a second mapping relationship of the threshold voltage interval; and establishing a process flow according to the corresponding threshold voltage adjustment process, the first mapping relationship being a mapping relationship between the threshold voltage interval and the MOS device type; and the second mapping relationship being a correspondence between the threshold voltage interval in the first mapping relationship and a threshold voltage adjustment process formed by at least one adjustment process selected from a preset process flow, the threshold voltage adjustment process causing a threshold voltage to be in the corresponding threshold voltage interval under the action of a total threshold voltage offset. According to the present disclosure, the difficulty in adjusting the threshold voltage is reduced.

First claim

What is claimed is:

1. A process manufacturing method, comprising:
determining a type of to-be-formed MOS device and a corresponding threshold voltage interval;
obtaining, according to the MOS device type and the corresponding threshold voltage interval, a corresponding threshold voltage adjustment process by querying a pre-configured first mapping relationship of the threshold voltage interval and a second mapping relationship of the threshold voltage interval;
establishing a process flow according to the corresponding threshold voltage adjustment process, wherein:
the first mapping relationship is a mapping relationship between the threshold voltage interval and the MOS device type, and
the second mapping relationship is a correspondence between the threshold voltage interval in the first mapping relationship and a threshold voltage adjustment process formed by at least one adjustment process selected from a preset process flow, the threshold voltage adjustment process causing a threshold voltage to be in the corresponding threshold voltage interval under the action of a total threshold voltage offset.

2. The process manufacturing method according to claim 1 , wherein in the step of establishing a process flow, the process flow further comprises an interface layer forming process and a high-k gate dielectric layer forming process that are sequentially performed, where the high-k gate dielectric layer forming process is performed before the adjustment process.

3. The process manufacturing method according to claim 1 , wherein:
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device type comprises one or more of an NMOS device and a PMOS device; and
the threshold voltage interval comprises at least one of:
a first threshold voltage, a second threshold voltage, a third threshold voltage, a fourth threshold voltage, a fifth threshold voltage, a sixth threshold voltage, a seventh threshold voltage, or an eighth threshold voltage,
where threshold voltages corresponding to the first threshold voltage, the second threshold voltage, the third threshold voltage, the fourth threshold voltage, the fifth threshold voltage, the sixth threshold voltage, the seventh threshold voltage, and the eighth threshold voltage increase progressively.

4. The process manufacturing method according to claim 1 , wherein in the step of obtaining a corresponding threshold voltage adjustment process by querying a pre-configured first mapping relationship of the threshold voltage interval and a second mapping relationship of the threshold voltage interval, in the second mapping relationship of the threshold voltage interval, the adjustment process comprises an electric dipole layer forming process, a work function layer forming process, and a work function layer plasma treatment process.

5. The process manufacturing method according to claim 4 , wherein:
the adjustment process in the preset process flow comprises: the electric dipole layer forming process, a first N-type work function layer forming process, a first P-type work function layer forming process, a second P-type work function layer forming process, a P-type work function layer plasma treatment process, a second N-type work function layer forming process, and an N-type work function layer plasma treatment process,
the first N-type work function layer forming process, the first P-type work function layer forming process, the second P-type work function layer forming process, and the second N-type work function layer forming process serving as the work function layer forming process, and the P-type work function layer plasma treatment process and the N-type work function layer plasma treatment process serving as the work function layer plasma treatment process.

6. The process manufacturing method according to claim 5 , wherein:
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a first threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the electric dipole layer forming process, the first N-type work function layer forming process, and the second N-type work function layer forming process; or
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a second threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the electric dipole layer forming process, the first N-type work function layer forming process, the second N-type work function layer forming process, and the N-type work function layer plasma treatment process; or
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a third threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the electric dipole layer forming process, the first P-type work function layer forming process, and the second N-type work function layer forming process; or
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a fourth threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the electric dipole layer forming process, the first P-type work function layer forming process, the second N-type work function layer forming process, and the N-type work function layer plasma treatment process; or
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a fifth threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the first P-type work function layer forming process and the second N-type work function layer forming process; or
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a sixth threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the first P-type work function layer forming process, the second N-type work function layer forming process, and the N-type work function layer plasma treatment process; or
in the step of determining a type of to-be-formed MOS device and a corresponding threshold voltage interval, the MOS device is an NMOS device, a threshold voltage interval corresponding to the NMOS device being a seventh threshold voltage; and
in the step of obtaining a corresponding threshold voltage adjustment process, the corresponding threshold voltage adjustment process comprises the first P-type work function layer forming process, the P-type work function layer plasma treatment process, and the N-type work function layer forming process; or
in the step of determ

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Yoo Abraham
• Jin Ying
• Jin Jisong

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D64/01

  Manufacture or treatment · CPC title