Storage system and method for optimizing write-amplification factor, endurance, and latency during a defragmentation operation

Patent metadata

Field	Value
Publication number	US-11809747-B2
Application number	US-202117558089-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.

First claim

What is claimed is:

1. A storage system comprising:
a memory; and
a controller coupled to the memory and configured to:
dynamically determine a size of a defragmentation unit based on an endurance of the memory;
dynamically determine a memory sense threshold based on the endurance of the memory;
analyze a logical block address range of data stored in the memory, wherein the logical block address range is analyzed in a resolution of the defragmentation unit; and
for each defragmentation unit:
determine a fragmentation level of the defragmentation unit by measuring a number of memory senses needed to read the defragmentation unit using the dynamically determined memory sense threshold;
determine if the fragmentation level is above a fragmentation threshold; and
in response to determining that the fragmentation level is above the defragmentation threshold, perform a defragmentation operation on the defragmentation unit.

2. The storage system of claim 1 , wherein a size of the defragmentation unit decreases with an age of the storage system.

3. The storage system of claim 1 , wherein the defragmentation unit with no fragmentation is readable by a single memory sense.

4. The storage system of claim 1 , wherein the controller is further configured to dynamically define the threshold based on endurance and performance tradeoffs.

5. The storage system of claim 1 , wherein the controller is further configured to perform the defragmentation operation independent of receiving a read command from a host.

6. The storage system of claim 1 , wherein the controller is further configured to perform the defragmentation operation without receiving an instruction from a host to perform the defragmentation operation.

7. The storage system of claim 1 , wherein the data comprises a file.

8. The storage system of claim 1 , wherein the controller is further configured to identify the logical block address range.

9. The storage system of claim 1 , wherein the logical block address range is identified by a host.

10. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

11. A method performed in a storage system comprising a memory, the method comprising:
dynamically determining a size of a defragmentation unit based on an endurance of the memory;
dynamically determining a memory sense threshold based on the endurance of the memory;
analyzing a logical block address range of data stored in the memory, wherein the logical block address range is analyzed in a resolution of the defragmentation unit; and
for each defragmentation unit:
determining a fragmentation level of the defragmentation unit by measuring a number of memory senses needed to read the defragmentation unit using the dynamically determined memory sense threshold;
determining if the fragmentation level is above a fragmentation threshold; and
in response to determining that the fragmentation level is above the defragmentation threshold, performing a defragmentation operation on the defragmentation unit.

12. The method of claim 11 , wherein the defragmentation unit with no fragmentation is readable by a single memory sense.

13. The method of claim 11 , wherein the data comprises a file.

14. A storage system comprising:
a memory;
means for dynamically determining a size of a defragmentation unit based on an endurance of the memory;
means for dynamically determining a memory sense threshold based on the endurance of the memory;
means for analyzing a logical block address range of data stored in the memory, wherein the logical block address range is analyzed in a resolution of the defragmentation unit; and
means for, for each defragmentation unit:
determining a fragmentation level of the defragmentation unit by measuring a number of memory senses needed to read the defragmentation unit using the dynamically determined memory sense threshold;
determining if the fragmentation level is above a fragmentation threshold; and
in response to determining that the fragmentation level is above the defragmentation threshold, performing a defragmentation operation on the defragmentation unit.

Assignees

• Western Digital Tech Inc

Inventors

• Zilberstein Einav
• Oshinsky Hadas
• Hayun Oren Ben
• Sela Rotem
• Lemberg Alex

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F12/0253 Primary

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title