Shiftable memory defragmentation

Patent metadata

Field	Value
Publication number	US-9542307-B2
Application number	US-201214381854-A
Country	US
Kind code	B2
Filing date	Mar 2, 2012
Priority date	Mar 2, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Shiftable memory that supports defragmentation includes a memory having built-in shifting capability, and a memory defragmenter to shift a page of data representing a contiguous subset of data stored in the memory from a first location to a second location within the memory to be adjacent to another page of stored data. A method of memory defragmentation includes defining an array in memory cells of the shiftable memory and performing a memory defragmentation using the built-in shifting capability of the shiftable memory to shift a data page stored in the array.

First claim

What is claimed is:

1. A shiftable memory supporting memory defragmentation, comprising:
a memory device to store data, the memory device having a built-in shifting capability to shift only data of a plurality of contiguous subsets of stored data corresponding to respective pages of data from a first location to a second location within the memory device, each page of the pages of data having a size that is smaller than a total size of the memory device, wherein the built-in shifting capability is to:
shift a first contiguous subset of the plurality of contiguous subsets to be adjacent a second contiguous subset of the plurality of contiguous subsets, and
following the shifting of the first contiguous subset, shift a group of contiguous subsets including the first and second contiguous subsets together to the second location; and

a memory defragmenter to shift the plurality of contiguous subsets using the built-in shifting capability of the memory device, the second location being adjacent to another page of stored data.

2. The shiftable memory of claim 1 , wherein the shift of the first contiguous subset comprises a page-sized shift.

3. The shiftable memory of claim 1 , wherein the memory device having built-in shifting capability provides a plurality of different page sizes, the pages of data having page sizes selected from the plurality of different page sizes.

4. A shiftable memory system comprising the shiftable memory of claim 1 , the shiftable memory system further comprising a controller to select the pages of data and to implement the shift of the plurality of contiguous subsets according to the memory defragmenter.

5. The shiftable memory system of claim 4 , wherein the controller comprises an augmented decoder to assert an output corresponding to each memory cell of a plurality of memory cells of a page of data within the memory.

6. The shiftable memory system of claim 4 , wherein the controller comprises the memory defragmenter.

7. The shiftable memory of claim 1 , wherein the built-in shifting capability is to shift the plurality of contiguous subsets of data without reading or writing of the data of the plurality of contiguous subsets of data by a resource external of the memory device.

8. The shiftable memory of claim 1 , wherein the built-in shifting capability is to shift the plurality of contiguous subsets of data without reading or writing of the data of the plurality of contiguous subsets of data by a processor external of the memory device.

9. A memory defragmentation system comprising:
a shiftable memory device comprising a plurality of memory cells, the shiftable memory device having built-in shifting capability to shift a plurality of contiguous subsets of data stored in the memory cells within the shiftable memory device, each contiguous subset of data of the plurality of contiguous subsets of data representing a page of data and having a size that is smaller than a total size of the shiftable memory device;
a memory defragmenter to perform a shift of the pages of data represented by the plurality of contiguous subsets of data from a first location in the shiftable memory device to a second location adjacent to another page of data stored in the shiftable memory device using the built-in shifting capability, wherein the built-in shifting capability is to:
shift a first contiguous subset of the plurality of contiguous subsets to be adjacent a second contiguous subset of the plurality of contiguous subsets, and
following the shifting of the first contiguous subset, shift a group of contiguous subsets including the first and second contiguous subsets together to the second location; and

a controller to select the pages of data and to implement the shift of the pages of data under direction of the memory defragmenter.

10. The memory defragmentation system of claim 9 , wherein the controller comprises an augmented decoder to assert an output corresponding to each memory cell of a plurality of memory cells of each page of data within the shiftable memory device.

11. The memory defragmentation system of claim 9 , wherein the shift of the pages of data performed by the memory defragmenter shifts each page of data of the pages of data until all of the pages of data are adjacent to one another.

12. The memory defragmentation system of claim 9 , wherein the built-in shifting capability is to shift the plurality of contiguous subsets of data without reading or writing of the data of the plurality of contiguous subsets of data by a resource external of the shiftable memory device.

13. A method of memory defragmentation using a shiftable memory device, the method comprising:
defining an array in memory cells of the shiftable memory device, the shiftable memory device having a plurality of memory cells and a built-in shifting capability to shift a plurality of contiguous subsets of data stored in the array from a first location to a second location, each contiguous subset of data of the plurality of contiguous subsets of data having a size that is less than a total size of the shiftable memory device, wherein the shifting of the plurality of contiguous subsets of data by the built-in shifting capability comprises:
shifting a first contiguous subset of the plurality of contiguous subsets to be adjacent a second contiguous subset of the plurality of contiguous subsets, and
following the shifting of the first contiguous subset, shifting a group of contiguous subsets including the first and second contiguous subsets together to the second location; and

performing a memory defragmentation by using the built-in shifting capability to shift data pages representing the plurality of contiguous subsets of data stored in the array from the first location in the shiftable memory device to the second location adjacent to another page of data stored in the shiftable memory device,
wherein the shifting of the plurality of contiguous subsets of data occurs entirely within the shiftable memory device and only data of the plurality of contiguous subsets of data is shifted.

14. The method of claim 13 , wherein the shiftable memory device provides a plurality of different page sizes, the data pages having sizes selected from the plurality of different page sizes.

15. The method of claim 13 , wherein the shift of each of the plurality of contiguous subsets of data comprises a page-sized shift, and wherein performing the memory defragmentation comprises shifting each data page of the data pages until all of the data pages are adjacent to one another.

16. The method of claim 15 , wherein shifting each data page comprises performing a sequential compaction of the data pages.

17. The method of claim 13 , wherein the shifting of the plurality of contiguous subsets of data by the built-in shifting capability is performed without reading or writing of the data of the plurality of contiguous subsets of data by a resource external of the shiftable memory device.

18. The method of claim 13 , wherein the shifting of the plurality of contiguous subsets of data by the built-in shifting capability is performed without reading or writing of the data of the plurality of contiguous subsets of data by a processor external of the shiftable memory device.

Assignees

• Karp Alan H
• Hewlett Packard Entpr Dev Lp

Inventors

• Karp Alan H

Classifications

• G06F12/023 Primary

  Free address space management · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/1036

  using data shift registers · CPC title

• G06F3/0608

  Saving storage space on storage systems · CPC title

• G06F2212/161

  Portable computer, e.g. notebook · CPC title