Storage system and method for quantifying storage fragmentation and predicting performance drop

Patent metadata

Field	Value
Publication number	US-11809736-B2
Application number	US-202117558014-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.

First claim

What is claimed is:

1. A storage system comprising:
a memory; and
a controller coupled to the memory and configured to:
generate a correlation between a number of senses to read the memory and a decrease in sequential read performance by:
sequentially writing a file to the memory; and
determining a number of senses to read the memory and a corresponding decrease in sequential read performance after each cycle of a plurality of cycles of random writes and sequential reads of the file, wherein a random write payload increases with each cycle;

determine a memory fragmentation level for each of a plurality of logical block address ranges of the memory according to (i) a number of memory senses required to read that logical block address range in its current state of fragmentation and (ii) a number of memory senses required to read that logical block address range assuming no fragmentation;
predict a decrease in sequential read performance caused by the memory fragmentation level for each of the plurality of logical block address ranges of the memory by referencing the number of memory senses required to read each logical block address range in its current state of fragmentation against the correlation;
prioritize the plurality of logical block address ranges based on the predicted decreases in sequential read performance, wherein a logical block address range having a relatively-greater predicted decrease in sequential read performance is prioritized over a logical block address range having a relatively-lower predicted decrease in sequential read performance; and
perform defragmentation operations based on the prioritization.

2. The storage system of claim 1 , wherein the controller is further configured to determine the memory fragmentation level using a logical-to-physical address map.

3. The storage system of claim 1 , wherein the predicted decrease in sequential read performance is used in a learning system.

4. The storage system of claim 1 , wherein each logical block address range comprises sequential logical block addresses that map to non-sequential physical block addresses in the memory.

5. The storage system of claim 1 , wherein the controller is further configured to determine the memory fragmentation level independent of receiving a read command from a host.

6. The storage system of claim 1 , wherein the defragmentation operations are performed without receiving an instruction from a host to perform the defragmentation operations.

7. The storage system of claim 1 , wherein the plurality of logical block address ranges correspond to a plurality of files.

8. The storage system of claim 1 , wherein the controller is further configured to identify the plurality of logical block address ranges.

9. The storage system of claim 1 , wherein the plurality of logical block address ranges are identified by a host.

10. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

11. The storage system of claim 1 , wherein the predicted decrease in sequential read performance is used in a warning mechanism.

12. The storage system of claim 1 , wherein the predicted decrease in sequential read performance is used in a system recovery operation.

13. In a storage system comprising a memory, a method comprising:
generating a correlation between a number of senses to read the memory and a decrease in sequential read performance by:
sequentially writing a file to the memory; and
determining a number of senses to read the memory and a corresponding decrease in sequential read performance after each cycle of a plurality of cycles of random writes and sequential reads of the file, wherein a random write payload increases with each cycle;

determining a memory fragmentation level for each of a plurality of logical block address ranges of the memory according to (i) a number of memory senses required to read that logical block address range in its current state of fragmentation and (ii) a number of memory senses required to read that logical block address range assuming no fragmentation;
predicting a decrease in sequential read performance caused by the memory fragmentation level for each of the plurality of logical block address ranges of the memory by referencing the number of memory senses required to read each logical block address range in its current state of fragmentation against the correlation;
prioritizing the plurality of logical block address ranges based on the predicted decreases in sequential read performance, wherein a logical block address range having a relatively-greater predicted decrease in sequential read performance is prioritized over a logical block address range having a relatively-lower predicted decrease in sequential read performance; and
performing defragmentation operations based on the prioritization.

14. The method of claim 13 , wherein the defragmentation operations are performed independent of receiving a read command from a host.

15. The method of claim 13 , wherein the defragmentation operations are performed without receiving a command from a host to perform the defragmentation operations.

16. The method of claim 13 , wherein the plurality of logical block address ranges correspond to a plurality of files.

17. A storage system comprising:
a memory;
means for generating a correlation between a number of senses to read the memory and a decrease in sequential read performance by:
sequentially writing a file to the memory; and
determining a number of senses to read the memory and a corresponding decrease in sequential read performance after each cycle of a plurality of cycles of random writes and sequential reads of the file, wherein a random write payload increases with each cycle;

means for determining a memory fragmentation level for each of a plurality of logical block address ranges of the memory according to (i) a number of memory senses required to read that logical block address range in its current state of fragmentation and (ii) a number of memory senses required to read that logical block address range assuming no fragmentation;
means for predicting a decrease in sequential read performance caused by the memory fragmentation level for each of the plurality of logical block address ranges of the memory by referencing the number of memory senses required to read each logical block address range in its current state of fragmentation against the correlation;
means for prioritizing the plurality of logical block address ranges based on the predicted decreases in sequential read performance, wherein a logical block address range having a relatively-greater predicted decrease in sequential read performance is prioritized over a logical block address range having a relatively-lower predicted decrease in sequential read performance; and
means for performing defragmentation operations based on the prioritization.

18. The storage system of claim 17 , further comprising means for performing defragmentation operations independent of receiving a read command from a host.

Assignees

• Western Digital Tech Inc

Inventors

• Zilberstein Einav
• Oshinsky Hadas
• Suliman Maayan
• Inbar Karin

Classifications

• G06F3/0653 Primary

  Monitoring storage devices or systems · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title