System architecture with secure data exchange

Patent metadata

Field	Value
Publication number	US-11809346-B2
Application number	US-202016947937-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	Nov 16, 2015
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

First claim

What is claimed is:

1. A system, comprising:
a first bus comprising a first physical transmission medium;
a second bus comprising a second physical transmission medium, the second physical transmission medium being physically separate from the first physical transmission medium;
a first peripheral coupled to the first bus and the second bus, the first peripheral to:
receive a first command from the first bus;
generate a random number responsive to the first command;
generate corruption indication data; and
transmit, via the second bus, the random number and the corruption indication data,
wherein packets of the corruption indication data are randomly interleaved with data packets of the random number; and

a second peripheral coupled to the first bus and the second bus, the second peripheral to access the random number via the second bus and generate a cryptographic key responsive to the random number.

2. The system of claim 1 , further comprising: a corruption detection module coupled to the second bus and is to detect data corruption using the corruption indication data.

3. The system of claim 1 , wherein the corruption indication data is appended to the random number.

4. The system of claim 1 , wherein the first peripheral is further to: initiate a transmission of the random number on the second bus; and initiate a transmission of the corruption indication data on the second bus.

5. The system of claim 1 , wherein the corruption indication data includes a cyclic redundancy check (CRC) code.

6. The system of claim 1 , wherein access to the random number is limited to the second bus.

7. The system of claim 1 , wherein the second bus is a synchronous bus.

8. A method comprising: receiving, at a first peripheral, a first command via a first bus having a first physical transmission medium; generating, via the first peripheral, a random number responsive to the first command; generating, via the first peripheral, corruption indication data corresponding to the random number; initiating, via the first peripheral, a transmission of the random number and the corruption indication data overa second bus having a second physical transmission medium, the second physical transmission medium being physically separate from the first physical transmission medium, wherein the transmission includes packets of corruption indication data randomly interleaved with data packets of the random number; and generating, via a second peripheral, a cryptographic key responsive to accessing the random number accessed via the second bus.

9. The method of claim 8 , further comprising detecting, via a corruption detection module coupled to the second bus, corrupted data responsive to the corruption indication data.

10. The method of claim 8 , wherein the transmission includes alternating data packets of the random number and the corruption indication data.

11. The method of claim 1 , wherein the initiating the transmission further comprises:
initiating a transmission of the random number over the second bus; and
initiating a transmission of the corruption indication data over the second bus.

12. The method of claim 8 , wherein the corruption indication data includes a cyclic redundancy check (CRC) code.

13. The method of claim 8 , further comprising preventing access through the first bus to data transmitted on the second bus.

14. A device comprising:
a system bus interface for coupling to a system bus and to receive a command via the system bus; and
a secure bus interface for coupling to a secure bus and to generate and transmit secure bus commands via the secure bus;
wherein the device is to:
determine that the command is to transmit sensitive data;
generate a random number in response to the command; and
initiate a transmission of the random number over the secure bus,
wherein the system bus and the secure bus each comprise a respective physical transmission medium that is separate from the other, and
wherein the secure bus interface to generate and randomly interleave data packets including the random number and integrity data packets for transmission via the secure bus.

15. The device of claim 14 , further comprising:
processing circuitry coupled to each of the system bus interface and the secure bus interface; and
memory coupled to the processing circuitry.

16. The system of claim 1 , wherein the second bus comprises:
a data bus;
a command bus; and
an error checking bus.

Assignees

• Atmel Corp
• Amtel Corp

Inventors

• Pean Guillaume
• Debout Vincent
• Maunier Marc

Classifications

• G06F13/20 Primary

  for access to input/output bus · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/4068

  Electrical coupling · CPC title