Configuring a device based on a dpa countermeasure

Patent metadata

Field	Value
Publication number	US-2016315760-A1
Application number	US-201615135024-A
Country	US
Kind code	A1
Filing date	Apr 21, 2016
Priority date	Apr 23, 2015
Publication date	Oct 27, 2016
Grant date	—

Abstract

Input signals may be received. Furthermore, a control signal controlling the implementation of a Differential Power Analysis (DPA) countermeasure may be received. One of the input signals may be transmitted as an output signal based on the control signal. A cryptographic operation may be performed based on the first output signal that is transmitted based on the control signal.

First claim

What is claimed is:

1 . A method comprising:
receiving a plurality of input signals; receiving a control signal controlling implementation of a Differential Power Analysis (DPA) countermeasure; in response to the control signal indicating to implement the DPA countermeasure, performing a cryptographic operation with a first cryptographic component and a second cryptographic component based on switching between an input signal from the plurality of input signals and a second input signal, from the plurality of input signals, that is associated with the DPA countermeasure; and in response to the control signal indicating to not implement the DPA countermeasure, performing a first cryptographic operation with the first cryptographic component without the second input signal associated with the DPA countermeasure and a second cryptographic operation with the second cryptographic component without the second input signal associated with the DPA countermeasure.

2 . The method of claim 1 , wherein performing the cryptographic operation with the first cryptographic component and the second cryptographic component in response to the control signal indicating to implement the DPA countermeasure comprises:
transmitting, from the first cryptographic component, a first output signal based on alternating a selection between an output of the second cryptographic component and the second input signal that is associated with the DPA countermeasure; and transmitting, from the second cryptographic component, an output signal based on alternating a selection between the first output signal of the first cryptographic component and the second input signal that is associated with the DPA countermeasure.

3 . The method of claim 1 , wherein the second input signal that is associated with the DPA countermeasure corresponds to a randomly generated number.

4 . The method of claim 1 , wherein performing the first cryptographic operation with the first cryptographic component without the second input signal associated with the DPA countermeasure and the second cryptographic operation with the second cryptographic component without the second input signal associated with the DPA countermeasure in response to the control signal indicating to not implement the DPA countermeasure comprises:
transmitting, from the first cryptographic component, an output signal based on a selection of an output of the first cryptographic component; and transmitting, from the second cryptographic component, another output signal based on a selection of another output of the second cryptographic component.

5 . The method of claim 1 , wherein the cryptographic operation corresponds to a round of an Advanced Encryption Standard (AES) operation.

6 . The method of claim 1 , wherein the cryptographic operation corresponds to a round of a block cipher operation.

7 . The method of claim 1 , wherein the control signal is received by a first and second selection units, and wherein each of the first and second selection unit is configured to transmit one of the plurality of input signals based on the control signal.

8 . An integrated circuit comprising:
a selection unit to:
receive a control signal that indicates whether a DPA countermeasure is to be implemented by the integrated circuit;
receive a plurality of input signals; and
output one of the plurality of input signals based on the control signal that indicates whether the DPA countermeasure is to be implemented by the integrated circuit; and
a cryptographic logic component to receive the output of the selection unit and to perform a cryptographic operation based on the output of the selection unit.

9 . The integrated circuit of claim 8 , wherein the plurality of input signals comprises a first input signal, a second input signal, and a third input signal, and wherein the outputting of one of the plurality of input signals comprises:
selecting the first input signal as the output of the selection unit when the control signal indicates that the DPA countermeasure is not to be implemented; and alternating a selection between the second input signal and the third input signal when the control signal indicates that the DPA countermeasure is to be implemented.

10 . The integrated circuit of claim 9 , wherein the alternating of the selection between the second input signal and the third input signal comprises selecting the second input signal as the output of the selection unit in response to a first round of the cryptographic operation and selecting the third signal as the output of the selection unit in response to a second round of the cryptographic operation subsequent to the first round.

11 . The integrated circuit of claim 9 , wherein the first input signal is an output of the cryptographic logic component, the second input signal is an output of a second cryptographic logic component, and the third input signal is a randomly generated number.

12 . The integrated circuit of claim 11 , wherein the randomly generated number is randomly generated in response to each round of a block cipher operation corresponding to the cryptographic operation.

13 . The integrated circuit of claim 11 , wherein the first cryptographic logic component and the second cryptographic logic component correspond to a round of an Advanced Encryption Standard (AES) operation.

14 . The integrated circuit of claim 8 , wherein the selection unit is a multiplexer.

15 . A system on a chip (SoC) comprising:
a cryptographic component controller to:
identify an operation;
determine if a DPA countermeasure is to be used for the operation; and
generate a control signal based on whether the DPA countermeasure is to be used for the operation; and
a cryptographic component to:
receive the control signal generated by the cryptographic component controller; and
provide the DPA countermeasure for the operation based on the control signal.

16 . The SoC of claim 15 , wherein the operation is to be performed by the SoC with the cryptographic component.

17 . The SoC of claim 15 , wherein the cryptographic component controller is further to:
identify a second operation and a third operation; determine if the DPA countermeasure is to be used for the second operation; and determine if the DPA countermeasure is to be used for the third operation;

18 . The SoC of claim 17 , wherein the cryptographic component controller is further to generate a second control signal in response to determining that the DPA countermeasure is not to be used for each of the second operation and the third operation, wherein the SoC further comprises:
an additional cryptographic component to receive the second control signal and to perform the second operation and the third operation based on the second control signal that is generated in response to determining that the DPA countermeasure is not to be used for each of the second operation and the third operation.

19 . The SoC of claim 17 , wherein the cryptographic component controller is further to generate a second control signal and a third control signal in response to determining that the DPA countermeasure is to be used for at least one of the second operation or the third operation, wherein the SoC further comprises:
a second cryptographic component to receive the second control signal and to perform the second operation based on the second control signal that is generated in response to determining that the DPA countermeasure is to be used for the second operation; and a third cryptographi

Assignees

• Cryptography Res Inc

Inventors

• Gori Christopher
• Rohatgi Pankaj

Classifications

• H04L2209/08

  Randomization, e.g. dummy operations or using noise · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F21/755

  with measures against power attack · CPC title

• H04L9/003 Primary

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• G06F21/72

  in cryptographic circuits · CPC title