Electronic circuit for controlling power

Patent metadata

Field	Value
Publication number	US-11809263-B2
Application number	US-202117476525-A
Country	US
Kind code	B2
Filing date	Sep 16, 2021
Priority date	Jan 3, 2019
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

An electronic circuit includes a converter and a controller. The converter outputs a first voltage for a first cluster and a second voltage for a second cluster. When a first power to be provided to the first cluster based on the first voltage is lower than a first available power of the first cluster and a second power to be provided to the second cluster based on the second voltage is higher than a second available power of the second cluster, the controller outputs a first interrupt signal such that a level of the second voltage is adjusted based on a sum of the first power and the second power and a first threshold value determined based on the first available power and the second available power.

First claim

What is claimed is:

1. A power management integrated circuit (PMIC) comprising:
a converter configured to:
output a first voltage supplied to a first cluster and a second voltage supplied to a second cluster, the first cluster and the second cluster including at least one first core and at least one second core respectively and being included in a System-on-Chip (SoC); and
output first information of a first current supplied to the first cluster and second information of a second current supplied to the second cluster; and

a controller configured to:
receive the first voltage, the second voltage, the first information, and the second information;
calculate a first power supplied to the first cluster based on the first voltage and the first information and a second power supplied to the second cluster based on the second voltage and the second information;
output a first interrupt signal to the SoC in response to the first power exceeding a first available power and a second interrupt signal to the SoC in response to the second power exceeding a second available power;
adjust the first available power based on the first power and/or the second power; and
increase the first available power in response to the second power being less than the second available power.

2. The PMIC of claim 1 , wherein the controller increases the first available power as much as a difference between the second available power and the second power.

3. The PMIC of claim 1 , wherein the controller maintains the second available power.

4. The PMIC of claim 1 , wherein the controller increases the first available power in response to the second power being less than the second available power and the first power being greater than the first available power.

5. The PMIC of claim 1 , wherein the controller outputs a third interrupt signal to the SoC in response to the first power being less than a first threshold and a fourth interrupt signal to the SoC in response to the second power being less than a second threshold.

6. The PMIC of claim 1 , wherein the converter is further configured to:
output a third voltage supplied to a third cluster and a third information of a third current supplied to the third cluster, the third cluster including at least one third core and being included in the SoC, and
receive the third voltage and the third information, calculate a third power based on the third voltage and the third information, output a third interrupt signal to the SoC in response to the third power exceeding a third available power, and adjust the second available power based on the second power and the third power.

7. The PMIC of claim 6 , wherein in response to the third power being less than the third available power, the controller increases the second available power.

8. A System-on-Chip (SoC) comprising:
a first cluster including at least one first core;
a second cluster including at least one second core, the at least one second core having a different performance and/or a different efficiency from a performance and/or an efficiency of the at least one first core;
a controller configured to:
control a first frequency of a first clock signal supplied to the first cluster to control a first power consumed by the first cluster based on a first available power;
control a second frequency of a second clock signal supplied to the second cluster to control a second power consumed by the second cluster based on a second available power; and
increase the first power beyond the first available power in response to the second power being less than the second available power.

9. The SoC of claim 8 , wherein the controller allows the first power being over the first available power as much as a power difference between the second available power and the second power.

10. The SoC of claim 8 , wherein in response to the second power being less than the second available power and the first power to be consumed by the first cluster being greater than the first available power, the controller allows the first power being over the first available power.

11. The SoC of claim 8 , wherein the controller limits:
the first power based on a first interrupt signal received from an external device in association with the first available power, and
the second power based on a second interrupt signal received from the external device in association with the second available power.

12. The SoC of claim 11 , wherein the controller interrupts limiting:
the first power based on a third interrupt signal received from the external device in association with a first threshold, and
the second power based on a fourth interrupt signal received from the external device in association with a second threshold.

13. A method of supplying power to a System-on-Chip (SoC) including a first cluster including at least one first core and a second cluster including at least one second core, the at least one second core having a different performance and/or a different efficiency from a performance and/or an efficiency of the at least one first core, the method comprising:
supplying a first power to the first cluster based on a first voltage and a first current;
supplying a second power to the second cluster based on a second voltage and a second current;
limiting the first power in response to the first power exceeding a first available power;
limiting the second power in response to the second power exceeding a second available power;
adjusting the first available power based on the second power; and
increasing the first available power in response to the second power being less than the second available power.

14. The method of claim 13 , further comprising increasing the first available power in response to both the second power being less than the second available power and the first power being greater than the first available power.

15. The method of claim 14 , wherein the increasing the first available power comprises: increasing the first available power as much as a difference between the second available power and the second power.

16. The method of claim 13 , wherein:
the SoC further includes a third cluster including at least one third core, and
the method further comprises:
supplying a third power to the third cluster based on a third voltage and a third current;
limiting the third power in response to the third power exceeding a third available power; and
adjusting the second available power based on the third power.

17. The method of claim 16 , wherein the adjusting the second available power based on the third power comprises increasing the second available power as much as a difference between the third available power and the third power in response to both the third power being less than the third available power and the second power to be supplied to the third cluster being greater than the third available power.

18. The method of claim 13 , further comprising:
in response to the first power being less than a first threshold, interrupting the limiting the first power in response to the first power exceeding a first available power; and
in response to the second power being less than a second threshold, interrupting the limiting the second power in response to the second power exceeding a second available power.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Donghee

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title