Crystalline multilayer structure, semiconductor device, and method of manufacturing crystalline structure

US11804519B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11804519-B2
Application numberUS-202117239931-A
CountryUS
Kind codeB2
Filing dateApr 26, 2021
Priority dateApr 24, 2020
Publication dateOct 31, 2023
Grant dateOct 31, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A crystalline multilayer structure having a high-quality crystalline layer and a semiconductor device employing such a crystalline multilayer structure are provided. A crystalline multilayer structure, including a first crystalline layer having a first crystal, and a second crystalline layer stacked on the first crystalline layer and having a second crystal, wherein the first crystal includes polycrystalline κ-Ga2O3 and the second crystal is a single crystal of a crystalline oxide.

First claim

Opening claim text (preview).

The invention claimed is: 1. A manufacturing method of manufacturing a crystalline multilayer structure, the manufacturing method comprising: providing a crystalline substrate; providing a stress relaxation layer on the crystalline substrate; and providing a crystalline oxide layer having a single crystal of a crystalline oxide on the stress relaxation layer, wherein the stress relaxation layer includes κ-Ga 2 O 3 polycrystal. 2. The manufacturing method according to claim 1 , wherein the crystalline substrate is a sapphire substrate. 3. The manufacturing method according to claim 1 , wherein the stress relaxation layer has an unevenness portion including concavities and/or convexities formed on at least a part of a surface of the stress relaxation layer. 4. The manufacturing method according to claim 3 , wherein the stress relaxation layer is provided by forming the unevenness portion on the crystalline substrate directly or via another layer, and then forming the stress relaxation layer on the unevenness portion. 5. The manufacturing method according to claim 4 , wherein the unevenness portion is formed by arranging a mask regularly on the crystalline substrate directly or via another layer. 6. The manufacturing method according to claim 5 , wherein the stress relaxation layer is formed on the mask. 7. The manufacturing method according to claim 5 , wherein the mask includes a metal oxide of a Group 4 metal of the Periodic Table. 8. The manufacturing method according to claim 7 , wherein the Group 4 metal of the Periodic Table is titanium, zirconium, or hafnium. 9. The manufacturing method according to claim 1 , wherein the crystalline oxide comprises at least gallium. 10. The manufacturing method according to claim 1 , wherein the crystalline oxide has a corundum structure. 11. The manufacturing method according to claim 1 , wherein the crystalline oxide layer has a dislocation density of 1×10 7 /cm 2 or less.

Assignees

Inventors

Classifications

  • Crystal orientation · CPC title

  • Polycrystalline · CPC title

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • Crystal orientations · CPC title

  • being crystalline insulating materials · CPC title

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What does patent US11804519B2 cover?
A crystalline multilayer structure having a high-quality crystalline layer and a semiconductor device employing such a crystalline multilayer structure are provided. A crystalline multilayer structure, including a first crystalline layer having a first crystal, and a second crystalline layer stacked on the first crystalline layer and having a second crystal, wherein the first crystal includes p…
Who is the assignee on this patent?
Flosfia Inc, Nat Institute For Material Science, Nat Inst Materials Science
What technology area does this patent fall under?
Primary CPC classification H10P14/2921. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 31 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).