Hybrid bonding structures and semiconductor devices including the same

Patent metadata

Field	Value
Publication number	US-11804462-B2
Application number	US-202117467973-A
Country	US
Kind code	B2
Filing date	Sep 7, 2021
Priority date	Sep 8, 2020
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

A hybrid bonding structure and a semiconductor including the hybrid bonding structure are provided. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste may include solder particles including at least one of In, Zn, SnBiAg alloy, or SnBi alloy, and ceramic particles. The solder paste may include a flux. The solder particles may include Sn(42.0 wt %)-Ag(0.4 wt %)-Bi(57.5−X) wt %, and the ceramic particles include CeO 2 (X) wt %, where 0.05≤X≤0.1.

First claim

What is claimed is:

1. A hybrid bonding structure, comprising:
a solder ball; and
a solder paste bonded to the solder ball,
wherein the solder paste includes
solder particles, the solder particles including at least one of In, Zn, SnBiAg alloy, or SnBi alloy,
a flux, and
ceramic particles,

wherein a boundary area between the solder ball and the solder paste has a modulus of elasticity in a range of about 42.0 GPa to about 45.0 GPa, and
wherein the solder particles include Sn(42.0 wt %)-Ag(0.4 wt %)-Bi(57.5−X) wt %, and the ceramic particles include CeO 2 (X) wt %, where 0.05≤X≤0.1.

2. The hybrid bonding structure of claim 1 , wherein the ceramic particles include at least one of La 2 O 3 , CeO 2 , SiC, ZrO 2 , TiO 2 , Y 2 O 3 , or AlN.

3. The hybrid bonding structure of claim 1 , wherein the ceramic particles are included in an amount of about 0.05 wt % to about 0.1 wt % of a total mass of the solder paste.

4. The hybrid bonding structure of claim 1 , wherein the hybrid bonding structure has a Poisson's ratio in a range of about 0.31 to about 0.35.

5. The hybrid bonding structure of claim 1 , wherein the hybrid bonding structure has a coefficient of thermal expansion in a range of about 14 μm/(m·K) to about 40 μm/(m·K).

6. The hybrid bonding structure of claim 1 , wherein the ceramic particles include one or more surfaces having etched irregularities thereof.

7. The hybrid bonding structure of claim 1 , wherein the ceramic particles each include a metal thin film configured to form an intermetallic compound on one or more surfaces of the ceramic particles.

8. The hybrid bonding structure of claim 7 , wherein the metal thin film includes at least one of Au, Ag, Sn, In, Cu, or Ni.

9. The hybrid bonding structure of claim 1 , wherein the solder ball includes at least one of Sn—Ag—Cu alloy, Sn—Bi alloy, Sn—Bi—Ag alloy, or Sn—Ag—Cu—Ni alloy.

10. A semiconductor device, comprising:
a printed circuit board;
a semiconductor chip; and
a hybrid bonding structure between the printed circuit board and the semiconductor chip,
wherein the hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball,
wherein the solder paste includes
solder particles, the solder particles including at least one of In, Zn, SnBiAg alloy, or SnBi alloy,
a flux, and
ceramic particles,

wherein a boundary area between the solder ball and the solder paste has a modulus of elasticity in a range of about 42.0 GPa to about 45.0 GPa, and
wherein the solder particles include Sn(42.0 wt %)-Ag(0.4 wt %)-Bi(57.5−X) wt %, and the ceramic particles include CeO 2 (X) wt %, where 0.05≤X≤0.1.

11. The semiconductor device of claim 10 , wherein the ceramic particles include at least one of La 2 O 3 , CeO 2 , SiC, ZrO 2 , TiO 2 , Y 2 O 3 , or AlN.

12. The semiconductor device of claim 10 , wherein the ceramic particles include about 0.05 wt % to about 0.1 wt % of a total mass of the solder paste.

13. The semiconductor device of claim 10 , wherein the hybrid bonding structure has a Poisson's ratio in a range of about 0.31 to about 0.35.

14. The semiconductor device of claim 10 , wherein the hybrid bonding structure has a coefficient of thermal expansion in a range of about 14 μm/(m·K) to about 40 μm/(m·K).

15. The semiconductor device of claim 10 , wherein the ceramic particles include one or more surfaces having etched irregularities thereof.

16. The semiconductor device of claim 10 , wherein the ceramic particles each include a metal thin film configured to form an intermetallic compound on one or more surfaces of the ceramic particles.

17. The semiconductor device of claim 16 , wherein the metal thin film includes at least one of Au, Ag, Sn, In, Cu, or Ni.

18. The semiconductor device of claim 10 , wherein the solder ball includes at least one of Sn—Ag—Cu alloy, Sn—Bi alloy, Sn—Bi—Ag alloy, or Sn—Ag—Cu—Ni alloy.

19. An electronic device comprising the semiconductor device of claim 10 .

20. A hybrid bonding structure, comprising:
a solder ball; and
a solder paste bonded to the solder ball,
wherein the solder paste includes
solder particles, the solder particles including at least one of In, Zn, SnBiAg alloy, or SnBi alloy,
a flux, and
ceramic particles, the ceramic particles including at least one of La 2 O 3 , CeO 2 , SiC, ZrO 2 , TiO 2 , Y 2 O 3 , or AlN,
wherein the ceramic particles are included in an amount of about 0.05 wt % to about 0.1 wt % of a total mass of the solder paste.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chu Kunmo
• Lee Junghoon
• Song Byonggwon

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07353

  changes in shapes · CPC title