Semiconductor-on-insulator transistor layout for radio frequency power amplifiers

Patent metadata

Field	Value
Publication number	US-11804435-B2
Application number	US-202017138609-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	Jan 3, 2020
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

A semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die includes at least one contact pad and a transistor including a first terminal formed within the active layer. A conduction path can include a plurality of first conduction path portions extending between the first terminal and the at least one contact pad and residing within a footprint of the at least one contact pad.

First claim

What is claimed is:

1. A semiconductor-on-insulator die comprising:
a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer;
at least one contact pad;
a transistor including a first terminal, the first terminal formed within the active layer; and
a conduction path including a plurality of first conduction path portions, the first conduction path portions extending in a direct vertical path from the first terminal to the at least one contact pad and residing within a footprint of the at least one contact pad.

2. The die of claim 1 wherein the conduction path includes a first via segment formed within the first via layer and a first metal segment formed within the first metal layer, wherein the surface area of an interface between the first via segment and the first terminal is at least 5 percent of the surface area of the first terminal.

3. The die of claim 2 wherein the first terminal substantially completely overlaps the first via segment.

4. The die of claim 2 further comprising a second metal layer and a second via layer, the second via layer between the first metal layer and the second metal layer, the conduction path further including a second via segment formed from the second via layer and a second metal segment formed from the second metal layer.

5. The die of claim 4 wherein the surface area of an interface between the first metal segment and the second via segment is at least 15 percent of the surface area of the first metal segment.

6. The die of claim 1 wherein the transistor is a field effect transistor and the first terminal is a source of the transistor.

7. The die of claim 1 wherein the conductive path further includes a plurality of second conduction path portions extending between the first terminal and the at least one contact pad and which reside at least partly outside of the footprint of the at least one contact pad.

8. The die of claim 1 wherein the footprint of the at least one contact pad overlaps with a footprint of the transistor.

9. The die of claim 8 wherein at least 50 percent of the first terminal falls within the footprint of the at least one contact pad.

10. The die of claim 1 wherein the transistor includes first and second sections, the at least one contact pad includes a first contact pad and a second contact pad, a footprint of the first contact pad overlaps with a footprint of the first section of the transistor, and a footprint of the second contact pad overlaps with a footprint of the second section of the transistor.

11. The die of claim 1 wherein the die is a flip-chip die and the first contact pad includes at least one contact bump.

12. A packaged module comprising:
a semiconductor-on-insulator die including a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, a first via layer between the active layer and the first metal layer, at least one contact pad, and a transistor including a first terminal, the first terminal formed within the active layer;
a module metal layer electrically connected to the at least one contact pad of the die;
a ground plane electrically connected to the module metal layer; and
a conduction path including a plurality of first conduction path portions, the first conduction path portions extending in a direct vertical path from the first terminal to the ground plane and residing within a footprint of the at least one contact pad.

13. The packaged module of claim 12 further comprising a module via layer between the module metal layer and the ground plane, and a module via segment formed within the module via layer, the conduction path further including the module via segment.

14. The packaged module of claim 13 wherein a module metal segment is formed within the module metal layer and included in the conduction path, and substantially the entire first terminal falls within a footprint of the module metal segment.

15. The packaged module of claim 12 wherein a module metal segment is formed within the module metal layer and included in the conduction path, the at least one contact pad includes first and second contact pads, and the module metal segment includes a first portion connected to the first contact pad and a second portion connected to the second contact pad, the footprint of the module metal segment including a footprint of the first portion and a footprint of the second portion.

16. A power amplifier system comprising:
a semiconductor-on-insulator die including a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, a first via layer between the active layer and the first metal layer, and at least one contact pad; and
a power amplifier configured to amplify a radio frequency signal and including a first transistor formed in the semiconductor-on-insulator die, the first transistor including a first terminal formed within the active layer, a conduction path including a plurality of first conduction path portions, the first conduction path portions extending in a direct vertical path from the first terminal to the at least one contact pad and residing within a footprint of the at least one contact pad.

17. The power amplifier system of claim 16 wherein the first transistor is a field effect transistor and the first terminal is a source terminal.

18. The power amplifier system of claim 17 wherein the power amplifier further includes a second transistor formed in the semiconductor-on-insulator die, the second transistor being a field effect transistor.

19. The power amplifier system of claim 18 wherein the first transistor is configured in a common source configuration and the second transistor is configured in a common gate configuration.

20. The power amplifier system of claim 16 wherein the conductive path further includes a plurality of second conduction path portions extending between the first terminal and the at least one contact pad and which reside at least partly outside of the footprint of the at least one contact pad.

Assignees

• Skyworks Solutions Inc

Inventors

• Liu Yang
• Lee Yong Hee
• Obkircher Thomas

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title