Circuits and methods for improved quality factor in a stack of transistors

Patent metadata

Field	Value
Publication number	US-2015171860-A1
Application number	US-201414536814-A
Country	US
Kind code	A1
Filing date	Nov 10, 2014
Priority date	Nov 13, 2013
Publication date	Jun 18, 2015
Grant date	—

Abstract

Circuits and method for improved quality factor in a stack of transistors. A switching device can include a plurality of field-effect transistors (FETs) implemented in a stack configuration. The switching device can further include a bias circuit having a distribution network that couples a bias input node to the gate of each FET. The distribution network can include a plurality of first nodes, with each first node connected to one or more of the gates through one or more respective resistive paths. The distribution network can further include one or more second nodes, with each second node connected to one or more of the first nodes through one or more respective resistive paths. At least some of the resistive paths can have resistance values selected to reduce loss of a radio-frequency (RF) signal when the FETs are in an OFF state.

First claim

What is claimed is:

1 . A switching device comprising:
a first terminal and a second terminal; a plurality of field-effect transistors (FETs) implemented in a stack configuration between the first terminal and the second terminal, each FET having a source, a drain and a gate, the FETs configured to be in an ON state or an OFF state to respectively allow or inhibit passage of a radio-frequency (RF) signal between the first and second terminals; and a bias circuit having a bias input node and a distribution network that couples the bias input node to the gate of each FET, the distribution network including a plurality of first nodes, each first node connected to one or more of the gates through one or more respective resistive paths, the distribution network further including one or more second nodes, each second node connected to one or more of the first nodes through one or more respective resistive paths, at least some of the resistive paths associated with the first nodes and the second nodes having resistance values selected to reduce loss of the RF signal when the FETs are in the OFF state.

2 . The switching device of claim 1 wherein the FET is implemented as a silicon-on-insulator (SOI) device.

3 . The switching device of claim 2 wherein the FET is implemented as a finger configuration device such that the gate includes a number of rectangular shaped gate fingers, each gate finger implemented between a rectangular shaped source finger of the source contact and a rectangular shaped drain finger of the drain contact.

4 . The switching device of claim 1 wherein the first terminal is an input terminal and the second terminal is an output terminal for the RF signal.

5 . The switching device of claim 1 wherein the bias input node is connected to one second node through a common resistance.

6 . The switching device of claim 5 wherein the one second node is connected to a plurality of first nodes through their respective inter-node resistances.

7 . The switching device of claim 6 wherein each of the plurality of second nodes is connected to a plurality of gates through their respective gate resistances.

8 . The switching device of claim 1 wherein each resistive path between the corresponding first node and the corresponding gate includes a gate resistor.

9 . The switching device of claim 8 wherein each gate resistor is configured to reduce loss of the RF signal to ground through parasitic capacitance associated with the gate resistor.

10 . The switching device of claim 9 wherein each gate resistor has a reduced value of DC resistance, the reduced DC resistance resulting in a higher effective resistance for the frequency of the RF signal.

11 . The switching device of claim 10 wherein the higher effective resistance of the gate resistors results in an increase in an overall resistance (R OFF ) of the switching device for the RF signal when the FETs are in the OFF state.

12 . The switching device of claim 11 wherein the increased R OFF results in a higher Q factor performance of the switching device.

13 . The switching device of claim 9 wherein each resistive path between the corresponding first node and the corresponding second node includes an additional resistor.

14 . The switching device of claim 13 wherein each of the additional resistors is configured to reduce loss of the RF signal to the bias input node, and to reduce loss of the RF signal between the first and second terminals.

15 . The switching device of claim 1 further comprising a source/drain bias circuit having a source/drain bias input node and a distribution network that couples the source/drain bias input node to the source/drain of each FET, the distribution network including a plurality of first nodes, each first node connected to one or more of the sources/drains through one or more respective resistive paths, the distribution network further including one or more second nodes, each second node connected to one or more of the first nodes through one or more respective resistive paths, at least some of the resistive paths associated with the first nodes and the second nodes having resistance values selected to reduce loss of the RF signal when the FETs are in the OFF state.

16 . The switching device of claim 1 further comprising a body bias circuit having a body bias input node and a distribution network that couples the body bias input node to the body of each FET, the distribution network including a plurality of first nodes, each first node connected to one or more of the bodies through one or more respective resistive paths, the distribution network further including one or more second nodes, each second node connected to one or more of the first nodes through one or more respective resistive paths, at least some of the resistive paths associated with the first nodes and the second nodes having resistance values selected to reduce loss of the RF signal when the FETs are in the OFF state.

17 . The switching device of claim 1 wherein the stack configuration includes the plurality of FETs being connected in series.

18 . The switching device of claim 17 wherein the plurality of FETs form a substantially continuous chain of FETs.

19 . A method for fabricating a radio-frequency (RF) switching device, the method comprising:
providing a semiconductor substrate; forming a switching circuit on the semiconductor substrate, the switching circuit including a plurality of field-effect transistors (FETs) implemented in a stack configuration, each FET having a source, a drain and a gate, the FETs configured to be in an ON state or an OFF state to respectively allow or inhibit passage of an RF signal through the stack; and forming a bias circuit on the semiconductor substrate, the bias circuit having a bias input node and a distribution network that couples the bias input node to the gate of each FET, the distribution network including a plurality of first nodes, each first node connected to one or more of the gates through one or more respective resistive paths, the distribution network further including one or more second nodes, each second node connected to one or more of the first nodes through one or more respective resistive paths, at least some of the resistive paths associated with the first nodes and the second nodes having resistance values selected to reduce loss of the RF signal when the FETs are in the OFF state.

20 . A radio-frequency (RF) switching module comprising:
a packaging substrate configured to receive a plurality of components; and a die mounted on the packaging substrate, the die having a switching circuit, the switching circuit including a plurality of field-effect transistors (FETs) implemented in a stack configuration, each FET having a source, a drain and a gate, the FETs configured to be in an ON state or an OFF state to respectively allow or inhibit passage of an RF signal through the stack, the switching circuit further including a bias circuit having a bias input node and a distribution network that couples the bias input node to the gate of each FET, the distribution network including a plurality of first nodes, each first node connected to one or more of the gates through one or more respective resistive paths, the distribution network further including one or more second nodes, each second node connected to one or more of the first nodes through one or more respective resistive paths, at least some of the resistive paths associated with the first nodes and the second nodes having resis

Assignees

• Skyworks Solutions Inc

Inventors

• Blin Guillaume Alexandre

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title