Strain relief trenches for epitaxial growth

US11804374B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11804374-B2
Application numberUS-202016949373-A
CountryUS
Kind codeB2
Filing dateOct 27, 2020
Priority dateOct 27, 2020
Publication dateOct 31, 2023
Grant dateOct 31, 2023

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

First claim

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What is claimed is: 1. A method, comprising: forming a plurality of trenches in a plurality of first portions of a substrate; and growing a gallium nitride (GaN) epitaxial layer in the plurality of trenches, wherein the GaN epitaxial layer comprises non-contiguous portions based on the GaN epitaxial layer being grown in the plurality of trenches and not being grown in one or more second portions of the substrate, wherein wall angles of tapered walls for each portion of the non-contiguous portions are a same angle, and wherein a first portion of the GaN epitaxial layer grown in a first trench, of the plurality of trenches, has a different width-to-height aspect ratio than a second portion of the GaN epitaxial layer grown in a second trench of the plurality of trenches. 2. The method of claim 1 , wherein the substrate comprises a silicon substrate. 3. The method of claim 1 , wherein forming the plurality of trenches comprises: forming the plurality of trenches based on one or more parameters, wherein the one or more parameters are based on at least one of: a diameter of the substrate, a thickness of the substrate, a thickness of the GaN epitaxial layer to be grown, or a material type of the substrate. 4. The method of claim 1 , wherein forming the plurality of trenches comprises: forming the plurality of trenches based on one or more parameters, wherein the one or more parameters comprise at least one of: a depth of a trench of the plurality of trenches, a width of a trench of the plurality of trenches, a length of a trench of the plurality of trenches, a spacing between two trenches of the plurality of trenches, a shape of a trench of the plurality of trenches, a quantity of the plurality of trenches, or a pattern of the plurality of trenches. 5. The method of claim 4 , wherein forming the plurality of trenches comprises: forming a first subset of the plurality of trenches based on a first set of parameters; and forming a second subset of the plurality of trenches based on a second set of parameters, wherein at least a subset of the first set of parameters is different from a subset of the second set of parameters. 6. The method of claim 1 , wherein forming the plurality of trenches comprises: forming the plurality of trenches to have tapered walls. 7. The method of claim 1 , wherein a wall angle range, of the wall angles, includes 10 degrees to 15 degrees past 90 degrees. 8. The method of claim 1 , wherein a top surface of the GaN epitaxial layer is higher than a top surface of the one or more second portions. 9. The method of claim 1 , wherein forming the plurality of trenches comprises: forming the plurality of trenches in in a grid pattern. 10. The method of claim 1 , wherein a height of the first portion of the GaN epitaxial layer is greater than a width of the first portion of the GaN epitaxial layer. 11. A method, comprising: forming a photoresist layer over a substrate; exposing the photoresist layer to form a pattern in the photoresist layer; performing, using the pattern in the photoresist layer, a wet chemical etch of the substrate to form a plurality of trenches in a plurality of first portions of the substrate; and growing an epitaxial layer in the plurality of trenches, wherein the epitaxial layer comprises non-contiguous portions based on the epitaxial layer being grown in the plurality of trenches and not being grown in one or more second portions of the substrate, wherein wall angles of tapered walls for each portion of the non-contiguous portions are a same angle, and wherein a first portion of the epitaxial layer grown in a first trench, of the plurality of trenches, has a different width-to-height aspect ratio than a second portion of the epitaxial layer grown in a second trench of the plurality of trenches. 12. The method of claim 11 , wherein growing the epitaxial layer comprises: growing the epitaxial layer using a molecular beam epitaxy (MBE) process. 13. The method of claim 11 , wherein growing the epitaxial layer comprises: growing the epitaxial layer using a metal organic chemical vapor deposition (MOCVD) process. 14. A wafer, comprising: a substrate comprising a plurality of first portions in which a plurality of trenches are formed; and a plurality of epitaxial regions grown in the plurality of trenches, wherein the plurality of epitaxial regions are non-contiguous portions of a gallium nitride (GaN) epitaxial layer based on the GaN epitaxial layer being grown in the plurality of trenches and not being grown in one or more second portions of the substrate, wherein a top surface of the GaN epitaxial layer is higher than a top surface of the one or more second portions, wherein wall angles of tapered walls for each portion of the non-contiguous portions are a same angle, and wherein a first portion of the GaN epitaxial layer grown in a first trench, of the plurality of trenches, has a different width-to-height aspect ratio than a second portion of the GaN epitaxial layer grown in a second trench of the plurality of trenches. 15. The wafer of claim 14 , further comprising: a buffer layer between the plurality of epitaxial regions and the plurality of trenches; a spacer layer between the plurality of epitaxial regions and the buffer layer; a channel layer between the plurality of epitaxial regions and the spacer layer; and a barrier layer between the plurality of epitaxial regions and the channel layer. 16. The wafer of claim 14 , wherein a depth of a first subset of the plurality of trenches and a depth of a second subset of the plurality of trenches are different depths. 17. The wafer of claim 14 , wherein a width of a first subset of the plurality of trenches and a width of a second subset of the plurality of trenches are different widths. 18. The wafer of claim 14 , wherein a spacing between a first subset of the plurality of trenches and a spacing between a second subset of the plurality of trenches are different spacings. 19. The wafer of claim 9 , wherein the substrate comprises: a silicon substrate, a silicon carbide substrate, or an aluminum oxide substrate. 20. The wafer of claim 14 , wherein the plurality of trenches are formed in a grid pattern.

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Classifications

  • for Group V materials or Group III-V materials · CPC title

  • Structure · CPC title

  • Nitrides · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • using chemical vapour deposition [CVD] · CPC title

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What does patent US11804374B2 cover?
Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/2905. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 31 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).