Signal converter device, dynamic element matching circuit, and dynamic element matching method

Patent metadata

Field	Value
Publication number	US-11799490-B2
Application number	US-202217720754-A
Country	US
Kind code	B2
Filing date	Apr 14, 2022
Priority date	Jul 22, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

First claim

What is claimed is:

1. A signal converter device, comprising:
a first digital to analog converter circuit comprising a plurality of components, wherein the first digital to analog converter circuit is configured to utilize the plurality of components to generate a first signal component of a first signal in response to a plurality of first bits;
a second digital to analog converter circuit configured to generate a second signal component of the first signal in response to a second bit, wherein weights corresponding to the plurality of first bits are higher than a weight corresponding to the second bit; and
a dynamic element matching circuit configured to generate an adjusted pointer signal in response to a pointer signal and the plurality of first bits in a previous period, in order to set corresponding relations between the plurality of components and the plurality of first bits.

2. The signal converter device of claim 1 , wherein the dynamic element matching circuit is configured to sum up the pointer signal in the previous period and the plurality of first bits in the previous period to adjust the pointer signal, in order to generate the adjusted pointer signal.

3. The signal converter device of claim 1 , wherein the dynamic element matching circuit comprises:
an arithmetic logic unit circuit configured to sum up the plurality of first bits in the previous period and the pointer signal in the previous period, in order to generate a second signal;
a register circuit configured to output the second signal to be the adjusted pointer signal according to a clock signal; and
a decoder circuit configured to decode the adjusted pointer signal to be a plurality of control signals, wherein the first digital to analog converter circuit is further configured to select the plurality of components according to the plurality of control signals.

4. The signal converter device of claim 3 , wherein the register circuit is configured to output the adjusted pointer signal after a successive approximation register analog to digital circuit generates the second bit in the previous period.

5. The signal converter device of claim 1 , further comprising:
a comparator circuit configured to generate a decision signal; and
a successive approximation register control logic circuit configured to generate the plurality of first bits and the second bit according to the decision signal.

6. The signal converter device of claim 5 , wherein, the dynamic element matching circuit is configured to sum up the pointer signal and the plurality of first bits in the previous period during a progress of the successive approximation register control logic circuit generating the second bit in the previous period, and is configured to output the adjusted pointer signal after the progress is completed.

7. The signal converter device of claim 5 , wherein the dynamic element matching circuit is configured to start summing up the pointer signal and the plurality of first bits in the previous period after the successive approximation register control logic circuit generates the plurality of first bits in the previous period.

8. The signal converter device of claim 1 , wherein the dynamic element matching circuit is configured to sum up the pointer signal and the plurality of first bits in the previous period during a progress of the second digital to analog converter circuit processing the second bit in the previous period, and is configured to output the adjusted pointer signal after the progress is completed.

9. The signal converter device of claim 1 , wherein the dynamic element matching circuit is configured to adjust the pointer signal based on a non-thermometer code mode.

10. The signal converter device of claim 1 , wherein the first digital to analog converter circuit is a non-thermometer code digital to analog converter circuit.

11. A dynamic element matching circuit, comprising:
an arithmetic logic unit circuit configured to sum up a plurality of most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal;
a register circuit configured to output the first signal to be an adjusted pointer signal according to a clock signal; and
a decoder circuit configured to decode the adjusted pointer signal to be a plurality of control signals, wherein the plurality of control signals are configured to set corresponding relations of a plurality of components of a first digital to analog converter circuits and the plurality of most significant bits, in order to utilize the plurality of components to convert the plurality of most significant bits.

12. The dynamic element matching circuit of claim 11 , wherein the arithmetic logic unit circuit is configured to sum up the pointer signal in the previous period and the plurality of most significant bits in the previous period during a progress of a successive approximation register analog to digital converter circuit generating a least significant bit of the digital code in the previous period.

13. The dynamic element matching circuit of claim 11 , wherein the first digital to analog converter circuit is a non-thermometer code digital to analog converter circuit.

14. The dynamic element matching circuit of claim 11 wherein the arithmetic logic unit circuit is configured to start summing up the pointer signal in the previous period and the plurality of most significant bits in the previous period after the first digital to analog converter circuit generates the plurality of most significant bits in the previous period.

15. The dynamic element matching circuit of claim 11 , wherein the arithmetic logic unit circuit is configured to sum up the pointer signal in the previous period and the plurality of most significant bits in the previous period during a progress of a second digital to analog converter circuit processing a least significant bit of the digital code in the previous period.

16. A dynamic element matching method, comprising:
summing up a plurality of most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal;
outputting the first signal to be an adjusted pointer signal according to a clock signal; and
decoding the adjusted pointer signal to be a plurality of control signals,
wherein the plurality of control signals are configured to set corresponding relations of a plurality of components of a first digital to analog converter circuits and the plurality of most significant bits, in order to utilize the plurality of components to convert the plurality of most significant bits.

17. The dynamic element matching method of claim 16 , wherein summing up the plurality of most significant bits of the digital code in the previous period and the pointer signal in the previous period, in order to generate the first signal comprises:
summing up the pointer signal in the previous period and the plurality of most significant bits in the previous period during a progress of a successive approximation register analog to digital converter circuit generating a least significant bit of the digital code in the previous period.

18. The dynamic element matching method of claim 16 , wherein summing up the plurality of most significant bits of the digital code in the previous period and the pointer signal in the previous period, in order to generate the first signal comprises:
starting summing up the pointer signal in the previous period and the plurality of most significant bits in the previous period after t

Assignees

• Realtek Semiconductor Corp

Inventors

• Lin Sheng-Hsiung

Classifications

• H03M1/066 Primary

  by continuously permuting the elements used, i.e. dynamic element matching · CPC title

• H03M1/682

  both converters being of the unary decoded type · CPC title

• H03M7/165

  Conversion to or from thermometric code · CPC title

• H03M3/468 Primary

  Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title