Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same

Patent metadata

Field	Value
Publication number	US-11799005-B2
Application number	US-202117346524-A
Country	US
Kind code	B2
Filing date	Jun 14, 2021
Priority date	Mar 11, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.

First claim

What is claimed is:

1. A memory cell, comprising:
spaced apart source and drain regions in a semiconductor substrate with a channel region of the semiconductor substrate extending there between;
a floating gate disposed above and insulated from a first portion of the channel region for controlling a conductivity of the first portion of the channel region, wherein the floating gate includes an upper surface having a concave shape that terminates at a side surface of the floating gate at a sharp edge;
a word line gate that includes:
a first portion disposed above and insulated from a second portion of the channel region for controlling a conductivity of the second portion of the channel region,
a second portion disposed at least partially above the floating gate, and
a notch facing the sharp edge of the floating gate adjacent to the word line gate; and

a coupling gate disposed above and insulated from the floating gate, wherein the coupling gate includes a lower surface that:
faces the upper surface of the floating gate,
has a shape matching the concave shape of the upper surface of the floating gate, and
is insulated from the upper surface of the floating gate by an insulation layer of uniform thickness.

2. The memory cell of claim 1 , wherein the second portion of the word line gate is further disposed at least partially above the coupling gate.

3. A memory cell, comprising:
spaced apart source and drain regions in a semiconductor substrate with a channel region of the semiconductor substrate extending there between;
a floating gate disposed above and insulated from a first portion of the channel region for controlling a conductivity of the first portion of the channel region, wherein the floating gate includes an upper surface having a concave shape that terminates at a side surface of the floating gate at a sharp edge;
a word line gate disposed above and insulated from a second portion of the channel region for controlling a conductivity of the second portion of the channel region;
a coupling gate disposed above and insulated from the floating gate, wherein the coupling gate includes a lower surface that:
faces the upper surface of the floating gate,
has a shape matching the concave shape of the upper surface of the floating gate, and
is insulated from the upper surface of the floating gate by an insulation layer of uniform thickness; and

an erase gate disposed above and insulated from the floating gate and the coupling gate, and including a notch facing the sharp edge of the floating gate.

4. The memory cell of claim 3 , wherein the erase gate is further disposed at least partially above the word line gate.

Assignees

• Silicon Storage Tech Inc

Inventors

• Xing leo
• Wang Chunming
• Liu Xian
• Do Nhan
• Song guo xiang

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H01L29/42328 Primary

  Electricity · mapped topic