Apparatus with voltage protection mechanism

Patent metadata

Field	Value
Publication number	US-11798935-B2
Application number	US-202217871681-A
Country	US
Kind code	B2
Filing date	Jul 22, 2022
Priority date	Dec 12, 2019
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

First claim

We claim:

1. A memory system, comprising:
a first high voltage (HV) circuit;
a second HV circuit;
a protection circuit electrically connected to the first HV circuit and the second HV circuit, the protection circuit including:
a first trigger circuit electrically connected to the first HV circuit;
a first silicon-controlled rectifier (SCR) connected to the first trigger circuit and having—
a first grounding transistor electrically connected between the first HV circuit and ground and further electrically connected to the first trigger circuit, wherein the first grounding transistor configured to dynamically control an electrical connection between the first HV circuit and the ground according to the first trigger circuit, and
a first connecting transistor electrically connected between the first trigger circuit and the second HV circuit and further electrically connected to the first grounding transistor in anti-parallel, wherein the first connecting transistor is configured to dynamically control an electrical connection between the first and second HV circuits;

a second trigger circuit electrically connected to the first HV circuit;
a second SCR (1) electrically connected to the second trigger circuit and (2) electrically connected to the first SCR in anti-parallel, the second SCR having—
a second grounding transistor electrically connected between the second HV circuit and the ground and further electrically connected to the second trigger circuit, wherein the second grounding transistor configured to dynamically control an electrical connection between the second HV circuit and the ground according to the second trigger circuit, and
a second connecting transistor electrically connected between the second trigger circuit and the first HV circuit and further electrically connected to the second grounding transistor in anti-parallel, wherein the second connecting transistor is configured to dynamically control an electrical connection between the first and second HV circuits.

2. A memory system, comprising:
a first high voltage (HV) circuit;
a second HV circuit;
a protection circuit electrically connected to the first HV circuit and the second HV circuit, the protection circuit including:
a first trigger circuit electrically connected to the first HV circuit;
a first silicon-controlled rectifier (SCR) connected to the first trigger circuit and having—
a first grounding transistor electrically connected between the first HV circuit and ground and further electrically connected to the first trigger circuit, wherein the first grounding transistor configured to dynamically control an electrical connection between the first HV circuit and the ground according to the first trigger circuit, and
a first connecting transistor electrically connected between the first trigger circuit and the second HV circuit and further electrically connected to the first grounding transistor in anti-parallel, wherein the first connecting transistor is configured to dynamically control an electrical connection between the first and second HV circuits;

a second trigger circuit electrically connected to the first HV circuit;
a second SCR (1) electrically connected to the second trigger circuit and (2) electrically connected to the first SCR in anti-parallel, the second SCR having—
a second grounding transistor electrically connected between the second HV circuit and the ground and further electrically connected to the second trigger circuit, wherein the second grounding transistor configured to dynamically control an electrical connection between the second HV circuit and the ground according to the second trigger circuit, and
a second connecting transistor electrically connected between the second trigger circuit and the first HV circuit and further electrically connected to the second grounding transistor in anti-parallel, wherein the second connecting transistor is configured to dynamically control an electrical connection between the first and second HV circuits;

wherein the first and second trigger circuits each includes:
at least one resistor coupled to at least one capacitor electrically connected between a corresponding one of the first and second HV circuits and the ground, wherein the at least one resistor and the at least one capacitor are tuned to detect a threshold change in a voltage level of the corresponding HV circuit; and
a triggering transistor coupled to the at least one resistor and the at least one capacitor, the triggering transistor configured to change operating states based on the threshold change.

3. The memory system of claim 2 , wherein:
the first and second grounding transistors are each configured to electrically connect the corresponding HV circuit to a grounding path based on an operating state of the corresponding triggering transistor; and
the first and second connecting transistors are each configured to electrically connect the first and second HV circuits based on an operating state of the corresponding grounding transistor.

4. The memory system of claim 2 , wherein:
the first and second grounding transistors are configured to be inactive and isolate the corresponding HV circuit from a grounding path when the corresponding triggering transistor is inactive; and
the first and second connecting transistors are each configured to electrically isolate the first and second HV circuits from each other based on inactive state of the corresponding grounding transistor.

5. A memory system, comprising:
a first high voltage (HV) circuit;
a second HV circuit;
a protection circuit electrically connected to the first HV circuit and the second HV circuit, the protection circuit including:
a first trigger circuit electrically connected to the first HV circuit;
a first silicon-controlled rectifier (SCR) connected to the first trigger circuit and having—
a first grounding transistor electrically connected between the first HV circuit and ground and further electrically connected to the first trigger circuit, wherein the first grounding transistor configured to dynamically control an electrical connection between the first HV circuit and the ground according to the first trigger circuit, and
a first connecting transistor electrically connected between the first trigger circuit and the second HV circuit and further electrically connected to the first grounding transistor in anti-parallel, wherein the first connecting transistor is configured to dynamically control an electrical connection between the first and second HV circuits;

a second trigger circuit electrically connected to the first HV circuit;
a second SCR (1) electrically connected to the second trigger circuit and (2) electrically connected to the first SCR in anti-parallel, the second SCR having—
a second grounding transistor electrically connected between the second HV circuit and the ground and further electrically connected to the second trigger circuit, wherein the second grounding transistor configured to dynamically control an electrical connection between the second HV circuit and the ground according to the second trigger circuit, and
a second connecting transistor electrically connected between the second trigger circuit and the first HV circuit and further electrically connected to the second grounding transistor in anti-parallel, wherein the second connecting transistor is configured to dynamically control an electrical connection between the first and second HV circuits;

wherein the first and second trigger circuits each have:
a trigger transistor having a control portion and configured to deactivate upon detecting the corresponding triggering condition, wherein the deactivation triggers the connection between the first and second HV circuits;
at least one capacitor operatively coupling the cont

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Furia Milind Nemchand
• Chaine Michael D
• Smith Eric J

Classifications

• H10D18/251

  Lateral thyristors · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title