Multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-11798744-B2
Application number	US-202217691607-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Mar 16, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A multilayer ceramic capacitor includes a multilayer body, and external electrodes on a portion of a side surface portion including four side surface of the multilayer body, and on a portion of a first main surface of the multilayer body. The first main surface includes first regions covered with the external electrodes and a second region exposed from the external electrodes. The first regions of the first main surface each include recesses therein. The recesses in each of the first regions each include a spherical curved wall surface. The recesses in each of the first regions each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a multilayer body including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the multilayer body further including a first main surface and a second main surface which oppose each other in a lamination direction, a first side surface and a second side surface which oppose each other in a length direction perpendicular or substantially perpendicular to the lamination direction, and a third side surface and a fourth side surface which oppose each other in a width direction perpendicular or substantially perpendicular to the lamination direction and the length direction; and
a plurality of external electrodes on a portion of a side surface including the four side surfaces, and on a portion of the first main surface; wherein
the first main surface further includes a plurality of first regions covered with the plurality of external electrodes and a second region exposed from the plurality of external electrodes;
the plurality of first regions of the first main surface each include a plurality of recesses therein;
the plurality of recesses in each of the plurality of first regions each include a spherical curved wall surface; and
the plurality of recesses in each of the plurality of first regions each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

2. The multilayer ceramic capacitor according to claim 1 , wherein, in each of the plurality of first regions, an area ratio occupied by openings of the plurality of recesses is about 52% or more.

3. The multilayer ceramic capacitor according to claim 1 , wherein
each of the plurality of external electrodes is also provided on a portion of the second main surface;
the second main surface further includes a plurality of third regions covered by the plurality of external electrodes and a fourth region exposed from the plurality of external electrodes;
the plurality of third regions of the second main surface each include a plurality of recesses therein;
the plurality of recesses in each of the plurality of third regions each include a spherical curved wall surface; and
the plurality of recesses in each of the plurality of third regions each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

4. The multilayer ceramic capacitor according to claim 3 , wherein, in each of the plurality of third regions, an area ratio occupied by openings of the plurality of recesses is about 52% or more.

5. The multilayer ceramic capacitor according to claim 3 , wherein
the fourth region, in addition to the plurality of third regions, includes a plurality of recesses provided therein;
the plurality of recesses in the fourth region each include a spherical curved wall surface; and
the plurality of recesses provided in the fourth region each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

6. The multilayer ceramic capacitor according to claim 5 , wherein, in the fourth region, an area ratio occupied by openings of the plurality of recesses is about 52% or more.

7. The multilayer ceramic capacitor according to claim 1 , wherein
each of the plurality of external electrodes is also provided on a portion of the third side surface;
the third side surface further includes a plurality of fifth regions covered by the plurality of external electrodes and a sixth region exposed from the plurality of external electrodes;
the plurality of fifth regions of the third side surface each include a plurality of recesses therein;
the plurality of recesses in each of the plurality of fifth regions each include a spherical curved wall surface; and
the plurality of recesses in each of the plurality of fifth regions each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

8. The multilayer ceramic capacitor according to claim 7 , wherein, in each of the plurality of fifth regions, an area ratio occupied by openings of the plurality of recesses is about 52% or more.

9. The multilayer ceramic capacitor according to claim 1 , wherein
each of the plurality of external electrodes is also provided on a portion of the fourth side surface;
the fourth side surface further includes a plurality of seventh regions covered by the plurality of external electrodes and an eighth region exposed from the plurality of external electrodes;
the plurality of seventh regions of the fourth side surface each include a plurality of recesses therein;
the plurality of recesses in each of the plurality of seventh regions each include a spherical curved wall surface; and
the plurality of recesses in each of the plurality of seventh regions each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

10. The multilayer ceramic capacitor according to claim 9 , wherein, in each of the plurality of seventh regions, an area ratio occupied by openings of the plurality of recesses is about 52% or more.

11. The multilayer ceramic capacitor according to claim 1 , wherein
the plurality of external electrodes include a first external electrode and a second external electrode;
the first external electrode is provided at least on a portion of the first side surface and a portion of the first main surface;
the second external electrode is provided at least on a portion of the second side surface and a portion of the first main surface; and
the plurality of first regions include a first region covered with the first external electrode in a vicinity of the first side surface, and a first region covered with the second external electrode in a vicinity of the second side surface.

12. The multilayer ceramic capacitor according to claim 1 , wherein
the plurality of external electrodes include a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode;
the first external electrode is provided at least on a portion of the first main surface, a portion of the first side surface, and a portion of the third side surface;
the second external electrode is provided at least on a portion of the first main surface, a portion of the first side surface, and a portion of the fourth side surface;
the third external electrode is provided at least on a portion of the first main surface, a portion of the second side surface, and a portion of the third side surface;
the fourth external electrode is provided at least on a portion of the first main surface, a portion of the second side surface, and a portion of the fourth side surface; and
the plurality of first regions include a region covered with the first external electrode, a region covered with the second external electrode, a region covered with the third external electrode, and a region covered with the fourth external electrode.

13. The multilayer ceramic capacitor according to claim 1 , wherein
the second region, in addition to the plurality of first regions, includes a plurality of recesses therein;
the plurality of recesses in the second region each include a spherical curved wall surface; and
the plurality of recesses provided in the second region each have an average inlet size of about 0.3 μm or more and about 10.5 μm or less.

14. The multilayer ceramic capacitor according to claim 13 , wherein, in the second region, an area ratio occupied by openings of the plurality of recesses is about 52% or more.

15. The multilayer ceramic capacitor according to claim 1 , wherein ceramic particles included in the plurality of dielectric layers have an average particle size of about 0.1 μ

Assignees

• Murata Manufacturing Co

Inventors

• Nishimura Ryo

Classifications

• H01G4/232 Primary

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/002 Primary

  Details · CPC title

• H01G4/005

  Electrodes · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title