Display device including a timing controller to supply an adjustment option value through a data clock signal line and a method of driving the same

Patent metadata

Field	Value
Publication number	US-11798495-B2
Application number	US-202217873365-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Nov 19, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A display device including: a timing controller configured to supply an adjustment option value through a data clock signal line during a first initialization period, and generate second data based on first data and a control signal and supply the second data through the data clock signal line during a data period; a data driver configured to generate an adjustment value based on the adjustment option value during the first initialization period, and generate third data based on the adjustment value and the second data and generate a data signal based on the third data during the data period; and a pixel configured to display an image based on the data signal.

First claim

What is claimed is:

1. A display device, comprising:
a timing controller configured to supply an adjustment option value through a data clock signal line during a first initialization period, and generate second data based on first data and a control signal and supply the second data through the data clock signal line during a data period;
a data driver configured to generate an adjustment value based on the adjustment option value during the first initialization period, and generate third data based on the adjustment value and the second data and generate a data signal based on the third data during the data period,
wherein the adjustment option value has two signal levels, and
wherein the second data has four signal levels, and
a pixel configured to display an image based on the data signal,
wherein the data driver stores the adjustment value and supplies the adjustment value to the timing controller through a feedback line during the first initialization period.

2. The display device according to claim 1 , wherein the data driver comprises:
a receiver configured to receive the adjustment option value and the second data through the data clock signal line, and generate a clock signal and frame data based on the adjustment option value and the second data; and
an image processor configured to generate the data signal based on the clock signal and the frame data.

3. The display device according to claim 2 , wherein the receiver comprises:
an equalizer controller configured to generate the adjustment value using the adjustment option value during the first initialization period;
an equalizer configured to generate the third data by compensating for the second data using the adjustment value during the data period; and
a clock recovery circuit configured to recover the clock signal based on the third data during the data period and a data recovery circuit configured to recover the frame data based on the third data during the data period.

4. The display device according to claim 3 , wherein the equalizer controller generates the adjustment value using a plurality of option codes included in the adjustment option value.

5. The display device according to claim 1 , wherein the timing controller comprises:
a memory configured to store the adjustment value supplied through the feedback line.

6. The display device according to claim 5 , wherein the timing controller supplies the adjustment value to the data driver through the data clock signal line during a second initialization period.

7. The display device according to claim 6 , wherein the adjustment value supplied through the data clock signal line has two signal levels.

8. The display device according to claim 6 , wherein the adjustment value supplied through the data clock signal line has four signal levels.

9. The display device according to claim 6 , wherein the data driver supplies a feedback signal to the timing controller through the feedback line when the stored adjustment value is deleted.

10. The display device according to claim 9 , wherein the timing controller supplies the adjustment value to the data driver through the data clock signal line in response to the feedback signal during the second initialization period.

11. A method of driving a display device including a timing controller and a data driver, the method comprising:
supplying, by the timing controller, an adjustment option value to the data driver through a data clock signal line during a first initialization period, wherein the adjustment option value has two signal levels;
generating, by the data driver, an adjustment value based on the adjustment option value during the first initialization period;
generating, by the timing controller, second data based on first data and a control signal and supplying the second data to the data driver through the data clock signal line during a data period, wherein the second data has four signal levels;
generating, by the data driver, third data based on the adjustment value and the second data and generating a data signal based on the third data during the data period;
displaying an image based on the data signal; and
supplying, by the data driver, the adjustment value to the timing controller through a feedback line during the first initialization period.

12. The method according to claim 11 , further comprising:
supplying, by the timing controller, the adjustment value to the data driver through the data clock signal line during a second initialization period.

13. The method according to claim 12 , wherein the adjustment value supplied through the data clock signal line has two signal levels.

14. The method according to claim 12 , wherein the adjustment value supplied through the data clock signal line has four signal levels.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Chae Hee
• Kim Jong Soo
• Kim Heen Dol
• Lee Ji Ye
• Jung Young Suk

Classifications

• G09G3/3291 Primary

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title