Data driver, display device having the same, and method of driving the display device

Patent metadata

Field	Value
Publication number	US-10950197-B2
Application number	US-201916569562-A
Country	US
Kind code	B2
Filing date	Sep 12, 2019
Priority date	Sep 21, 2018
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A data driver of a display device includes an equalizer and an equalizer controller. The equalizer controller calculates a lock time during a training enable signal is in an active state while sequentially changing a set signal applied to the equalizer to one option code selected from among a plurality of option codes and provides an option code corresponding to a set lock time among the option codes to the equalizer as the set signal.

First claim

What is claimed is:

1. A data driver comprising:
an equalizer to output an equalizer output signal in response to a transmission signal and a set signal;
a clock and data recovery circuit to recover a clock signal and a data signal based on the equalizer output signal;
a lock detector to output a lock signal based on the equalizer output signal and the clock signal;
a reset detector to detect a training pattern included in the transmission signal to output a reset signal;
a training control circuit to output a training enable signal; and
an equalizer controller to output the set signal based on the lock signal, the reset signal, and the training enable signal, wherein the equalizer controller is to calculate a lock time during an active state of the training enable signal while sequentially changing the set signal applied to the equalizer to one option code selected from among a plurality of option codes and to provide an option code corresponding to a set lock time selected from among the plurality of option codes to the equalizer as the set signal when the training enable signal is deactivated.

2. The data driver of claim 1 , wherein the lock time is a time period from a time point at which the reset signal is enabled to a time point at which the lock signal is enabled.

3. The data driver of claim 1 , wherein the equalizer controller is to provide an option code having a lowest lock time selected from among the plurality of option codes to the equalizer as the set signal.

4. The data driver of claim 1 , wherein the reset detector is to output the reset signal enabled at a start time point of the training pattern included in the transmission signal.

5. The data driver of claim 1 , wherein the training enable signal is transited to the active state by the training control circuit when a set time elapses after a power source voltage begins to be supplied.

6. The data driver of claim 1 , wherein the equalizer controller comprises:
a logic circuit to receive the training enable signal, the lock signal, and the reset signal to output a lock time signal;
a selection signal generator to output a selection signal in response to the reset signal;
a plurality of lock time counter circuits, respectively corresponding to the plurality of option codes, wherein the plurality of lock time counter circuits is to be enabled in response to the selection signal and to output a plurality of count signals corresponding to a pulse width of the lock time signal; and
a set signal output circuit to output the option code corresponding to a count signal having a lowest value selected from among the plurality of count signals output from the plurality of lock time counter circuits as the set signal.

7. The data driver of claim 6 , wherein each of the lock time counter circuits comprises:
a counter to output the count signal; and
a switch to provide the lock time signal from the logic circuit to the counter in response to the selection signal, wherein the counter is to output the count signal corresponding to the pulse width of the lock time signal applied thereto through the switch.

8. The data driver of claim 1 , wherein the clock and data recovery circuit comprises:
a clock recovery circuit to receive the equalizer output signal and to output the clock signal; and
a data recovery circuit to recover the equalizer output signal to the data signal in synchronization with the clock signal.

9. The data driver of claim 8 , wherein the clock recovery circuit comprises:
a phase detector to detect a difference in phase between the equalizer output signal and the clock signal;
a charge pump to generate a control current according to the detected phase difference;
a loop filter to generate a control voltage corresponding to the control current; and
a voltage-controlled oscillator to output the clock signal having a frequency corresponding to the control voltage, and to set a frequency of the clock signal to an initialization level in response to the reset signal.

10. A display device comprising:
a display panel comprising a plurality of gate lines, a plurality of data lines, and a plurality of pixels, each pixel of the plurality of pixels being connected to a corresponding gate line selected from among the plurality of gate lines and a corresponding data line of the data lines;
a gate driver to drive the gate lines;
a data driver to drive the data lines; and
a timing controller to control the gate driver and the data driver in response to a control signal and an image signal, and to convert the image signal and the control signal to a transmission signal, and to transmit the transmission signal to the data driver, the data driver comprising:
an equalizer to output an equalizer output signal in response to the transmission signal and a set signal;
a clock and data recovery circuit to recover a clock signal and a data signal based on the equalizer output signal;
a lock detector to output a lock signal based on the equalizer output signal and the clock signal;
a reset detector to detect a training pattern included in the transmission signal to output a reset signal;
a training control circuit to output a training enable signal; and
an equalizer controller to output the set signal based on the lock signal, the reset signal, and the training enable signal, wherein the equalizer controller is to calculate a lock time during an active state of the training enable signal while sequentially changing the set signal applied to the equalizer to one option code of a plurality of option codes and to provide an option code corresponding to a set lock time selected from among the plurality of option codes to the equalizer as the set signal when the training enable signal is deactivated.

11. The display device of claim 10 , wherein the lock time is a time period from a time point at which the reset signal is enabled to a time point at which the lock signal is enabled.

12. The display device of claim 10 , wherein the equalizer controller is to provide an option code having a lowest lock time selected from among the plurality of option codes to the equalizer as the set signal.

13. The display device of claim 10 , wherein the equalizer controller comprises:
a logic circuit to receive the training enable signal, the lock signal, and the reset signal to output a lock time signal;
a selection signal generator to output a selection signal in response to the reset signal;
a plurality of lock time counter circuits, respectively corresponding to the option codes, wherein the plurality of lock time counter circuits is to be enabled in response to the selection signal, and to output a plurality of count signals corresponding to a pulse width of the lock time signal; and
a set signal output circuit to output the option code corresponding to a count signal having a lowest value selected from among the plurality of count signals output from the lock time counter circuits.

14. The display device of claim 13 , wherein each of the plurality of lock time counter circuits comprises:
a counter to output the count signal; and
a switch to provide the lock time signal from the logic circuit to the counter in response to the selection signal, wherein the counter is to output the count signal corresponding to the pulse width of the lock time signal applied thereto through the switch.

15. The display device of claim 10 , wherein the clock and data recovery circuit comprises:
a phase detector to detect a difference in phase between the equalizer output signal and the clock signal;
a charge pump to generate a control current according to the detecte

Assignees

• Samsung Display Co Ltd

Inventors

• Pyun Kihyun
• Kang Keunoh
• Kang Moonshik
• Ahn Gwangsoo
• Lee Dae-Sik

Classifications

• G09G2310/0272

  Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title