Pixel circuitry and operation for memory-containing electronic display

Patent metadata

Field	Value
Publication number	US-11798481-B2
Application number	US-202117164758-A
Country	US
Kind code	B2
Filing date	Feb 1, 2021
Priority date	May 8, 2018
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

First claim

What is claimed is:

1. An electronic display, comprising:
a memory disposed in an active area of the electronic display or disposed in integrated circuitry of the electronic display that is outside of the active area, wherein at least a portion of the memory is configured to store a plurality of bits indicative of a value within a data range;
a switch, disposed in the active area, that selectively provides an electrical signal in response to the plurality of bits stored in the memory;
a light-modulating device disposed on the active area, wherein the light-modulating device is configured to emit light based at least in part on the electrical signal; and
display driver circuitry disposed outside of the active area, wherein the display driver circuitry is configured to cause output of each first binary state bit of the plurality of bits before each second binary state bit of the plurality of bits, and wherein the first binary state bit is different from the second binary state bit.

2. The electronic display of claim 1 , wherein the plurality of bits comprises a first bit, a second bit, and a third bit, and wherein the display driver circuitry is configured to:
generate a first control signal to write the first bit, the second bit, and the third bit at a same time to the memory; and
generate a second control signal to cause the second bit to output from the memory before the first bit and third bit.

3. The electronic display of claim 1 , wherein the first binary state bit corresponds to a “1” bit.

4. The electronic display of claim 3 , wherein the display driver circuitry generates control signals to output the plurality of bits based at least in part on a bit-plane clock characterized by monotonically increasing time periods.

5. The electronic display of claim 1 , wherein the memory is associated with a pixel, and wherein the portion of the memory is less than an entirety of the memory.

6. The electronic display of claim 1 , wherein the value corresponds to a first color channel, and wherein the memory comprises unused memory configured to store “0” bits or data for a second color channel.

7. The electronic display of claim 1 , comprising a pixel comprising a current source, the memory, the switch, and the light-modulating device, wherein the current source generates the electrical signal for transmission to the light-modulating device.

8. The electronic display of claim 1 , wherein the display driver circuitry is configured to load different portions of the memory corresponding to different light-modulating devices at a same time.

9. A sub-pixel of a particular color in an electronic display, comprising:
a first terminal configured to receive a first voltage signal;
a second terminal configured to receive a second voltage signal;
a switch that transmits a current generated based on the first voltage signal and the second voltage signal when turned on by an image data control signal;
a memory that:
stores, in parallel in response to a first control signal, a plurality of bits indicative of a value within a data range, wherein the plurality of bits comprises a first bit, a second bit, and a third bit; and
outputs, in response to a second control signal, the second bit as the image data control signal before outputting the first bit and the third bit; and

a light-emitting diode configured to emit light in response to the current.

10. The sub-pixel of claim 9 , wherein the first voltage signal comprises a data voltage, and wherein the second voltage signal comprises a system voltage.

11. The sub-pixel of claim 9 , comprising a current source configured to generate the current based at least in part on the first voltage signal and the second voltage signal.

12. The sub-pixel of claim 9 , wherein the memory is configured to bit-wise transmit the first bit and the third bit to generate the image data control signal.

13. An electronic display, comprising:
a first sub-pixel, wherein the first sub-pixel corresponds to a first color channel, wherein the first sub-pixel comprises:
a first memory configured to store a first plurality of bits indicative of a first value within a first data range used to communicate image data of the first color channel; and
first driver circuitry configured to receive the first plurality of bits from the first memory, wherein the first driver circuitry is configured to cause a first light-emitting diode to emit light at least in part by generating a first control signal based at least in part on the first plurality of bits to cause transmission of an electrical signal through the first light-emitting diode; and

display driver circuitry, wherein the first plurality of bits comprises a first bit, a second bit, and a third bit, wherein the display driver circuitry is configured to:
generate a second control signal to at least partially cause storage of the first bit, the second bit, and the third bit in the first memory at a same time; and
generate a third control signal to cause the second bit to output from the first memory before the first bit and third bit.

14. The electronic display of claim 13 , comprising a row driver configured to generate control signals to coordinate output of reordered data from the first memory, a second memory, or both.

15. The electronic display of claim 14 , wherein, for the first sub-pixel, the reordered data comprises the first plurality of bits in a different order than input into the first memory.

16. The electronic display of claim 14 , wherein the first sub-pixel is configured to be programmed with a first signal indicative of the first value at a first time.

17. The electronic display of claim 13 , wherein the display driver circuitry is configured generate a plurality of control signals to cause the output of the first bit and the third bit after the second bit.

18. The electronic display of claim 17 , wherein the display driver circuitry generates the plurality of control signals in accordance with time periods of a bit-plane clock.

19. The electronic display of claim 13 , comprising:
an active area comprising a row of pixels, wherein the row of pixels comprises the first sub-pixel and a second sub-pixel, wherein the first sub-pixel is configured to emit light in response to first image data to present a first image frame, wherein the first image data comprises the first plurality of bits; and
a controller configured to transmit the first image data to the first sub-pixel at a first time and configured to transmit second image data to the second sub-pixel at a second time, wherein the second image data comprises a second plurality of bits;
wherein the first sub-pixel comprises:
a first current source configured to generate a first current;
a first organic light-emitting diode configured to emit the light in response to the first current;

wherein the second sub-pixel comprises:
a second current source configured to generate a second current;
a second organic light-emitting diode configured to emit the light in response to the second current; and

wherein transmitting the first image data to the first sub-pixel or transmitting the second image data to the second sub-pixel is arbitrated by a multiplexing control signal.

20. The electronic display of claim 16 , comprising:
a second sub-pixel, wherein the second sub-pixel corresponds to a second color channel, wherein the second sub-pixel comprises:
a second memory configured to store a second plurality of bits indicative of a second value within a second data range used to comm

Assignees

• Apple Inc

Inventors

• Lin Yingkan
• Kuo Tien-Chien
• Wang Bilin
• Jeon Kanghoon
• Knez Ivan
• Huang Chun-Yao

Classifications

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G2300/0439

  Pixel structures · CPC title