Ledge-free display

Patent metadata

Field	Value
Publication number	US-2016126231-A1
Application number	US-201414529663-A
Country	US
Kind code	A1
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

This disclosure provides systems, methods and apparatus for a ledge-free display. In one aspect, row driver circuits and column driver circuits may be provided from the backside of the display to reduce the size of the bezel around the display and eliminate the need for a bonding ledge for a ledge-free display.

First claim

What is claimed is:

1 . A device comprising:
a display including a display unit associated with one or more transistors at a non-viewing side of the display; a bonding pad on the non-viewing side of the display; an interconnect on the non-viewing side of the display, coupled to the bonding pad; and a via on the non-viewing side of the display, the via coupled to the bonding pad by the interconnect on the non-viewing side of the display, the via further coupled to the interconnect to an internal interconnect of the display.

2 . The device of claim 1 , wherein the internal interconnect is coupled with the one or more transistors.

3 . The device of claim 2 , wherein the one or more transistors includes a transistor associated with the display unit, wherein the internal interconnect is coupled with a first terminal of the transistor, and the transistor has a second terminal coupled with an electrode of the display unit.

4 . The device of claim 2 , wherein the one or more transistors includes a first row driver transistor associated with a row driver circuit, the first row driver transistor coupled with a second row driver transistor associated with the row driver circuit, wherein the second row driver transistor is behind a second display unit.

5 . The device of claim 1 , further comprising:
a circuit board bonded to the bonding pad, the circuit board comprising a chip and a conductive path between the chip and the bonding pad.

6 . The device of claim 1 , wherein the display includes a viewing side associated with a substrate.

7 . The device of claim 6 , wherein the display unit is between the substrate and the one or more transistors.

8 . The device of claim 7 , wherein the bonding pad is between the circuit board and the one or more transistors.

9 . The device of claim 8 , further comprising:
a hermetic seal between the bonding pad and the one or more transistors.

10 . The device of claim 9 , wherein the via is outside of the hermetic seal.

11 . The device of claim 1 , further comprising:
a processor that is capable of communicating with the display device, the processor being configured to process image data; and a memory device that is capable of communicating with the processor.

12 . The device of claim 11 , further comprising:
a driver circuit capable of sending at least one signal to the display; and a controller capable of sending at least a portion of the image data to the driver circuit.

13 . The device of claim 11 , further comprising:
an image source module capable of sending the image data to the processor, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter.

14 . The device of claim 11 , further comprising:
an input device capable of receiving input data and to communicate the input data to the processor.

15 . A device comprising:
a display including an array of display units, each display unit associated with one or more transistors behind the associated display units; an array of bonding pads on a non-viewing side of the display; a plurality of interconnects on the non-viewing side of the display, each of the interconnects coupled to one of the bonding pads; and a plurality of vias on the non-viewing side of the display, each via coupled to one of the interconnects coupled to one of the bonding pads, and each via coupled to an associated internal interconnect of the display.

16 . The device of claim 15 , further comprising:
a circuit board bonded to the array of bonding pads.

17 . The device of claim 16 , wherein the circuit board includes a chip, and wherein the circuit board includes conductive paths between the chip and the array of bonding pads.

18 . The device of claim 15 , wherein the one or more transistors includes a transistor associated with the display unit, wherein the associated internal interconnect is coupled with a first terminal of the transistor, and the transistor has a second terminal coupled with an electrode of the display unit.

19 . A device comprising:
a display including a first display unit; a bonding pad on a non-viewing side of the display; a circuit board coupled with the bonding pad; and an internal interconnect of the display coupled with the bonding pad.

20 . The device of claim 19 , further comprising:
a first display unit transistor having a first terminal, a second terminal, and a control terminal, wherein the internal interconnect is coupled with the first terminal, and the second terminal is coupled with an electrode of the first display unit.

21 . The device of claim 20 , further comprising:
a row driver transistor having an output coupled with the control terminal of the control terminal of the first display unit transistor, the row driver transistor and the first display unit transistor both being between the display unit and the bonding pad.

22 . The device of claim 20 , wherein the circuit board is a chip-on-flex (COF).

Assignees

• Qualcomm Mems Technologies Inc

Inventors

• Endisch Denis
• Kim Cheonhong
• Van Lier Wilhelmus Johannes Robertus

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10H29/10

  Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 (active-matrix LED displays H10H29/30) · CPC title

• H01L27/124

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic