Storage controller, storage system and method of operating the same

Patent metadata

Field	Value
Publication number	US-11797381-B2
Application number	US-202217816554-A
Country	US
Kind code	B2
Filing date	Aug 1, 2022
Priority date	Jan 17, 2020
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

First claim

What is claimed is:

1. A storage controller comprising:
an error estimation circuit configured to receive a plurality of data, to estimate an error level of the plurality of data, and to generate error information;
a decision circuit configured to receive the plurality of data, to perform a first operation on the plurality of data, and to generate decision data;
an error correction circuit configured to receive the decision data, to correct an error on the decision data, and to generate error correction data; and
a selection circuit configured to select one among the decision data and the error correction data,
wherein the error information has a first value when the error estimation circuit estimates the error level of the plurality of data to be equal to or higher than a first level, and the error information has a second value when the error estimation circuit estimates the error level of the plurality of data to be less than the first level, and
wherein the selection circuit is configured to select the error correction data when the error information has the first value, and to select the decision data when the error information has the second value.

2. The storage controller of claim 1 , further comprising a plurality of channels configured to simultaneously receive the plurality of data from a plurality of external memories.

3. The storage controller of claim 1 , wherein the error estimation circuit includes a syndrome operation circuit configured to generate syndrome data, and
wherein the error estimation circuit estimates the error level of the plurality of data based on the syndrome data.

4. The storage controller of claim 1 , wherein the first operation performed by the decision circuit is a logical operation based on bits of the plurality of data.

5. The storage controller of claim 1 , wherein the first operation performed by the decision circuit is a hard decision operation on bits of the plurality of data, and
wherein the hard decision operation is a majority decision logical operation on corresponding bits of the plurality of data.

6. The storage controller of claim 1 , wherein the first operation performed by the decision circuit is a soft decision operation on bits of the plurality of data, and
wherein the soft decision operation indicates locations where uncorrected errors are likely to exist.

7. The storage controller of claim 1 , wherein the error correction circuit receives the error information, and is enabled or disabled based on the error information.

8. A storage controller comprising:
an error estimation circuit configured to receive a plurality of data, to estimate an error level of the plurality of data, and to generate error information;
a hard decision circuit configured to receive the plurality of data, to perform a first operation on the plurality of data, and to generate hard decision data;
a soft decision circuit configured to receive the plurality of data, to perform a second operation on the plurality of data, and to generate soft decision data;
an error correction circuit configured to receive the hard decision data and the soft decision data, and to generate error correction data using the hard decision data and the soft decision data; and
a selection circuit configured to select one among the hard decision data and the error correction data,
wherein the error information has a first value when the error estimation circuit estimates the error level of the plurality of data to be equal to or higher than a first level, and the error information has a second value when the error estimation circuit estimates the error level of the plurality of data to be less than the first level, and
wherein the selection circuit is configured to select the error correction data when the error information has the first value, and to select the hard decision data when the error information has the second value.

9. The storage controller of claim 8 , wherein the error correction circuit corrects an error on the hard decision data based on the soft decision data to generate the error correction data.

10. The storage controller of claim 8 , further comprising a plurality of channels configured to simultaneously receive the plurality of data from a plurality of external memories.

11. The storage controller of claim 8 , wherein the error estimation circuit includes a syndrome operation circuit configured to generate syndrome data, and
wherein the error estimation circuit estimates the error level of the plurality of data based on the syndrome data.

12. The storage controller of claim 8 , wherein the first operation is a logical operation based on bits of the plurality of data.

13. The storage controller of claim 8 , wherein the error correction circuit receives the error information, and is enabled or disabled based on the error information.

14. A solid state drive (SSD) comprising:
a plurality of nonvolatile memories; and
a controller coupled to the plurality of nonvolatile memories through a plurality of channels,
wherein the controller includes:
an error estimation circuit configured to receive a plurality of data, to estimate an error level of the plurality of data, and to generate error information, the error information having a first value when the error estimation circuit estimates the error level of the plurality of data to be equal to or higher than a first level, and the error information having a second value when the error estimation circuit estimates the error level of the plurality of data to be less than the first level;
a decision circuit configured to receive the plurality of data, to perform a first operation on the plurality of data, and to generate decision data;
an error correction circuit configured to receive the decision data, to correct an error on the decision data, and to generate error correction data; and
a selection circuit configured to select the error correction data when the error information has the first value, and to select the decision data when the error information has the second value.

15. The SSD of claim 14 , further comprising the plurality of channels configured to simultaneously receive the plurality of data from the plurality of nonvolatile memories.

16. The SSD of claim 14 , wherein the first operation is a hard decision operation on bits of the plurality of data, and
wherein the hard decision operation is a majority decision logical operation on corresponding bits of the plurality of data.

17. The SSD of claim 14 , wherein the error correction circuit receives the error information, and is enabled or disabled based on the error information.

18. The SSD of claim 14 , wherein the first operation performed by the decision circuit is a logical operation based on bits of the plurality of data.

19. The SSD of claim 14 , wherein the error estimation circuit includes a syndrome operation circuit configured to generate syndrome data, and
wherein the error estimation circuit estimates the error level of the plurality of data based on the syndrome data.

20. The SSD of claim 14 , wherein the plurality of nonvolatile memories form a Redundant Array of Independent Disks (RAID).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Na Hanbyeul
• Jang Jaehun
• Son Hongrak

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title