Storage device and method for foggy and fine programming

Patent metadata

Field	Value
Publication number	US-11797202-B2
Application number	US-202016918521-A
Country	US
Kind code	B2
Filing date	Jul 1, 2020
Priority date	Dec 24, 2019
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

First claim

What is claimed is:

1. A memory controller configured to control a memory device including a memory block coupled to physical word lines each including a plurality of pages, the memory controller comprising:
a program sequence information storage configured to store program sequence information of the plurality of pages, which includes information about a sequence of foggy program operations and fine program operations to be performed on the plurality of pages, wherein the foggy program operations and the fine program operations are alternately performed in units of a single page, and pages on which each of the foggy program operations and the fine program operations in a continuous sequence are performed are respectively included in different word lines; and
a program controller configured to control the memory device, in response to a power off event occurring while a program operation is performed on a selected page among the plurality of pages, based on the program sequence information, alternately to perform the fine program operations on to-be-completed pages and to perform the foggy program operations for a dummy program operation on boundary pages,
wherein the to-be-completed pages are pages on which the foggy program operations have been completed and on which the fine program operations have not yet been performed, and the boundary pages are pages on which the dummy program operation storing dummy data is to be performed, and
wherein when the fine program operations on the to-be-completed pages are completed, the dummy program operation is completed while only the foggy programs are performed on the boundary pages and the fine programs are not performed on the boundary pages.

2. The memory controller according to claim 1 , wherein the program operation includes:
a foggy program operation of programming memory cells included in the plurality of pages so that each of the memory cells has a threshold voltage corresponding to any one of intermediate states respectively corresponding to a plurality of states, and
a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each of the memory cells has a threshold voltage corresponding to any one of the plurality of states.

3. The memory controller according to claim 1 , wherein a number of the boundary pages corresponds to a number of the plurality of pages.

4. The memory controller according to claim 1 , wherein the program controller is further configured to store power off information after the dummy program operation is completed.

5. The memory controller according to claim 4 , further comprising a power off information storage configured to store the power off information.

6. The memory controller according to claim 4 , wherein the power off information includes at least one of information about the selected page on which the program operation is interrupted due to the power off event, information about the boundary pages, and information about pages included in a physical word line on which a program operation is to be performed in a sequence subsequent to the physical word line including the selected page.

7. A memory device comprising:
a memory block coupled to physical word lines each including a plurality of pages;
a peripheral circuit configured to perform a program operation of storing data in the plurality of pages;
a control logic configured to control the peripheral circuit,
wherein the program operation includes:
a foggy program operation of programming memory cells included in the plurality of pages so that each of the memory cells has a threshold voltage corresponding to any one of intermediate states respectively corresponding to a plurality of states, and
a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each of the memory cells has a threshold voltage corresponding to any one of the plurality of states,

wherein the control logic controls the peripheral circuit to perform foggy program operations and fine program operations alternately in units of a single page, and pages on which each of the foggy program operations and the fine program operations in a continuous sequence are performed are respectively included in different word lines,
wherein the control logic controls the peripheral circuit to further alternately perform, in response to a power off event in which power supply to the memory device is interrupted, based on the program sequence information, the fine program operations on each of to-be-completed pages and the foggy program operations for a dummy program operation on boundary pages,
wherein the to-be-completed pages are pages on which the foggy program operations have been completed and on which the fine program operations have not yet been performed, and the boundary pages are pages on which the dummy program operation storing dummy data is to be performed, and
wherein when the fine program operations on the to-be-completed pages are completed, the dummy program operation is completed while only the foggy programs are performed on the boundary pages and the fine programs are not performed on the boundary pages.

8. The memory device according to claim 7 ,
wherein the foggy program operation and the fine program operation each includes a plurality of program loops,
wherein each of the plurality of program loops includes a program voltage application operation and a verify operation, and
wherein a level of a verify voltage to be used in the verify operation of the foggy program operation is less than a level of a verify voltage to be used in the verify operation of the fine program operation.

9. The memory device according to claim 7 , wherein the plurality of pages included in each physical word line is coupled in common to the physical word line.

10. The memory device according to claim 7 , wherein each of the physical word lines comprises logical word lines respectively coupled to the plurality of pages.

11. The memory device according to claim 7 , wherein the dummy program operation is an operation to store dummy data in the boundary pages.

12. The memory device according to claim 11 , wherein a number of the boundary pages corresponds to a number of the plurality of pages.

13. A storage device comprising:
a memory device comprising a memory block coupled to physical word lines each including a plurality of pages; and
a memory controller configured to control the memory device such that, in response to a power off event occurring while a program operation is performed on a selected page among the plurality of pages, based on the program sequence information, fine program operations are performed on to-be-completed pages and foggy program operations for a dummy program operation on boundary pages alternately, wherein the to-be-completed pages are pages on which the foggy program operations have been completed and on which the fine program operations have not yet been performed and the boundary pages are pages on which the dummy program operation storing dummy data is to be performed,
wherein the program operation includes:
a foggy program operation of programming memory cells included in the plurality of pages so that each of the memory cells has a threshold voltage corresponding to any one of intermediate states respectively corresponding to a plurality of states, and
a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each of the memory cells has a threshold voltage corresponding to any one of the pluralit

Assignees

• Sk Hynix Inc

Inventors

• Ji Seung Gu
• Rho Jun Rye

Classifications

• G06F3/0634 Primary

  by changing the state or mode of one or more devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title