Storage device and forming method having a strip-shaped bitline contact structure

Patent metadata

Field	Value
Publication number	US-11792973-B2
Application number	US-202117444908-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Jul 28, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.

First claim

What is claimed is:

1. A method for forming a memory device, comprising:
providing a semiconductor substrate, forming a plurality of discrete active regions extending along a first direction in the semiconductor substrate, the plurality of active regions being isolated by an isolation layer, forming two parallel word lines extending along a second direction in each active region and a corresponding isolation layer, the two parallel word lines dividing each active region into a drain region located between the two parallel word lines and source regions located outside of the word lines respectively, and a first acute angle being provided between the first direction and the second direction;
forming a plurality of parallel mask patterns extending along a third direction on the semiconductor substrate by adopting a self-alignment multi-pattern process, providing an opening between the adjacent mask patterns, the opening exposing surfaces of a plurality of the drain regions and corresponding isolation layers in the third direction;
using the plurality of parallel mask patterns as masks, etching the drain region and the corresponding isolation layer along the opening to form a plurality of parallelly distributed trenches in the drain region and the corresponding isolation layer;
filling the trench with a conductive layer to form a strip-shaped bitline contact structure;
breaking the strip-shaped bitline contact structure to form a plurality of bitline contact blocks connected with corresponding drain regions; and
forming a bitline connecting the plurality of bitline contact blocks along a direction perpendicular to the second direction.

2. The method for forming a memory device of claim 1 , wherein a second acute angle is provided between the third direction and the first direction.

3. The method for forming a memory device of claim 2 , wherein a third acute angle is provided between the third direction and the second direction, the second acute angle being greater than the first acute angle and the third acute angle, and the sum of the first acute angle, the second acute angle, and the third acute angle being 180 degrees.

4. The method for forming a memory device of claim 3 , wherein the first acute angle ranges from 60 degrees to 75 degrees, the second acute angle ranges from 65 degrees to 85 degrees, and the third acute angle ranges from 35 degrees to 45 degrees.

5. The method for forming a memory device of claim 4 , wherein the first acute angle is 69 degrees, the second acute angle is 70 degrees, and the third acute angle is 41 degrees.

6. The method for forming a memory device of claim 1 , wherein said forming a plurality of parallel mask patterns extending along a third direction on the semiconductor substrate by adopting a self-alignment multi-pattern process, providing an opening between the adjacent mask patterns, the opening exposing surfaces of a plurality of the drain regions and corresponding isolation layers in the third direction comprises:
forming a hard mask layer on the substrate, and forming a plurality of parallel first patterns extending along the third direction on the hard mask layer;
forming a sidewall material layer on the top and a sidewall surface of the first pattern and on the surface of the hard mask layer between the adjacent first patterns;
forming a second pattern on the sidewall material layer, the second pattern filling up the space between the first patterns;
removing the sidewall material layer on the top of the first pattern and between the first pattern and the second pattern, and forming the opening between the first pattern and the second pattern; and
etching the hard mask layer along the opening, thus the bottom of the opening exposes the surfaces of the plurality of drain regions and the corresponding isolation layers in the third direction, and the remaining of the hard mask layers on both sides of the opening are the adjacent mask patterns.

7. The method for forming a memory device of claim 6 , wherein when etching the hard mask layer along the opening, an etching rate of the drain region and the hard mask layer is greater than that of the isolation protective layer.

8. The method for forming a memory device of claim 7 , wherein the isolation protective layer is provided on the surface of the word line, when forming the trench, an etching selection ratio of the drain region to the isolation protective layer being 5:1-15:1.

9. The method for forming a memory device of claim 6 , wherein a material of the second pattern is at least one of: silicon oxynitride, silicon carbonitride, polysilicon, silicon oxide, amorphous silicon, and amorphous carbon.

10. The method for forming a memory device of claim 6 , wherein a material of the second pattern is different from a material of the sidewall material layer.

11. The method for forming a memory device of claim 6 , wherein the sidewall material layer is formed by one of following processes:
an atomic layer deposition process, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, a thermal chemical vapor deposition method, or a high-density plasma chemical vapor deposition process.

12. The method for forming a memory device of claim 6 , wherein a thickness of the sidewall material layer is smaller than an interval between adjacent first patterns.

13. The method for forming a memory device of claim 1 , wherein the forming of the bitline contact block includes a first part and a second part located on the first part, the first part being embedded in the trench formed in the drain region, the second part protruding from the surface of the first part, the second part extending along a direction perpendicular to the second direction, and a width of the second part in the second direction or the third direction being smaller than the width of the first part in the second direction or the third direction.

14. The method for forming a memory device of claim 1 , wherein a material of the conductive layer is one of following:
doped polysilicon, tungsten, aluminum, copper, titanium, silver, gold, platinum, and nickel.

15. The method for forming a memory device of claim 1 , wherein a surface of the conductive layer is flush with a surface of the active region or higher than the surface of the active region.

16. A memory device, comprising:
a semiconductor substrate, a plurality of discrete active regions extending along a first direction being formed in the semiconductor substrate, the plurality of active regions being isolated by an isolation layer, two parallel word lines extending along a second direction being formed in each active region and the corresponding isolation layer, the two word lines dividing each active region into a drain region located between the two word lines and source regions located outside of the word lines respectively, and a first acute angle being provided between the first direction and the second direction; and
a plurality of parallel mask patterns extending along a third direction being formed on the semiconductor substrate, the mask pattern being formed by adopting a self-alignment multi-pattern process, an opening being provided between the adjacent mask patterns, the opening exposing the surfaces of a plurality of the drain regions and the corresponding isolation layers in the third direction, and the mask patterns serving as masks when the drain region and the corresponding isolation layer are subsequently etched, and a plurality of parallelly distributed trenches are formed in the drain region and the corresponding isolation layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Huang Juanjuan
• Wang Lingxiang

Classifications

• H10B12/34 Primary

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/485

  Bit line contacts · CPC title