Semiconductor device

Patent metadata

Field	Value
Publication number	US-11791386-B2
Application number	US-202217895054-A
Country	US
Kind code	B2
Filing date	Aug 24, 2022
Priority date	Feb 9, 2021
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first gate structure disposed on the semiconductor substrate;
a first source region and a first drain region, wherein the first source region and the first drain region are disposed in the semiconductor substrate and located at two opposite sides of the first gate structure in a first direction respectively;
a second gate structure disposed on the semiconductor substrate;
a second source region and a second drain region, wherein the second source region and the second drain region are disposed in the semiconductor substrate and located at two opposite sides of the second gate structure in the first direction respectively;
first field plates disposed on the semiconductor substrate, wherein each of the first field plates is partly located above the first gate structure and partly located between the first gate structure and the first drain region, and the first gate structure is electrically connected with at least one of the first field plates; and
second field plates disposed on the semiconductor substrate, wherein each of the second field plates is partly located above the second gate structure and partly located between the second gate structure and the second drain region, and the second source region is electrically connected with at least one of the second field plates.

2. The semiconductor device according to claim 1 , wherein the first source region and the second source region are located between the first gate structure and the second gate structure in the first direction.

3. The semiconductor device according to claim 1 , wherein the first source region is electrically connected with the second source region.

4. The semiconductor device according to claim 1 , wherein the first source region is electrically connected with at least one of the first field plates, the second gate structure is electrically connected with at least one of the second field plates, the first field plate electrically connected with the first gate structure is electrically separated from the first field plate electrically connected with the first source region, and the second field plate electrically connected with the second gate structure is electrically separated from the second field plate electrically connected with the second source region.

5. The semiconductor device according to claim 4 , wherein the first field plate electrically connected with the first source region is electrically connected with the second field plate electrically connected with the second source region.

6. The semiconductor device according to claim 1 , further comprising:
a doped region disposed in the semiconductor substrate and located between the first source region and the second source region in the first direction.

7. The semiconductor device according to claim 6 , wherein the first field plates and the second field plates comprise a mirror symmetry symmetrical about the doped region.

8. The semiconductor device according to claim 1 , wherein the first field plates are repeatedly arranged in a second direction orthogonal to the first direction, and the second field plates are repeatedly arranged in the second direction.

9. A semiconductor device, comprising:
a semiconductor substrate;
a first gate structure disposed on the semiconductor substrate;
a first source region and a first drain region, wherein the first source region and the first drain region are disposed in the semiconductor substrate and located at two opposite sides of the first gate structure in a first direction respectively;
a second gate structure disposed on the semiconductor substrate;
a second source region and a second drain region, wherein the second source region and the second drain region are disposed in the semiconductor substrate and located at two opposite sides of the second gate structure in the first direction respectively;
first field plates disposed on the semiconductor substrate, wherein each of the first field plates is partly located above the first gate structure and partly located between the first gate structure and the first drain region, and the first gate structure is electrically connected with at least one of the first field plates; and
second field plates disposed on the semiconductor substrate, wherein each of the second field plates is partly located above the second gate structure and partly located between the second gate structure and the second drain region, the second source region is electrically connected with at least one of the second field plates, and a number of the first field plates is different from a number of the second field plates.

Assignees

• United Microelectronics Corp

Inventors

• Wang Yi-Chieh
• Lai Po-Chun
• Lin Ke-Feng
• Kuo Chen-An
• Jhou Ze-Wei

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D64/112 Primary

  comprising multiple field plate segments · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D84/835

  comprising LDMOS · CPC title