Semiconductor device packaging warpage control

Patent metadata

Field	Value
Publication number	US-11791283-B2
Application number	US-202117230098-A
Country	US
Kind code	B2
Filing date	Apr 14, 2021
Priority date	Apr 14, 2021
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device packaging panel, the method comprising:
forming a panel having an active side and a backside, the panel including a plurality of semiconductor die encapsulated with an encapsulant, an active surface of the semiconductor die exposed on the active side of the panel; and
attaching a warpage control carrier onto the backside of the panel, the warpage control carrier including a first electroactive element configured for substantially flattening the panel while a first control voltage is applied to the first electroactive element.

2. The method of claim 1 , further comprising forming a planar-sensitive layer over the plurality of semiconductor die at the active side of the panel while the panel is substantially flattened on the warpage control carrier.

3. The method of claim 1 , wherein the warpage control carrier further includes a sensor element configured to provide an output voltage indicative of panel warpage while the warpage control carrier is attached to the backside of the panel.

4. The method of claim 3 , wherein the first control voltage applied to the first electroactive element is based on the output voltage of the sensor element.

5. The method of claim 3 , wherein the sensor element is characterized as a strain gauge element configured to provide the output voltage.

6. The method of claim 1 , wherein the first electroactive element of the warpage control carrier is in the form of a linear strip or a circular strip.

7. The method of claim 1 , wherein the warpage control carrier further includes a second electroactive element configured to receive a second control voltage, the first electroactive element located in a first region of the warpage control panel and the second electroactive element located in a second region of the warpage control panel.

8. The method of claim 7 , wherein the warpage control carrier is further configured for substantially flattening the panel while the first control voltage is applied to the first electroactive element and the second control voltage is applied to the second electroactive element.

9. The method of claim 7 , wherein the first electroactive element located in the first region of the warpage control panel is oriented orthogonal to the second electroactive element located in the second region of the warpage control panel.

10. The method of claim 1 , wherein forming the panel further comprises removing the carrier substrate after encapsulating with an encapsulant to expose the active side of the panel.

11. A method of manufacturing a semiconductor device packaging panel, the method comprising:
forming a panel having an active side and a backside, the panel including:
placing a plurality of semiconductor die on a first side of a carrier substrate;
encapsulating with an encapsulant the plurality semiconductor die and exposed portions of the first side of the carrier substrate;

attaching a warpage control carrier onto the backside of the panel, the warpage control carrier including a first electroactive element; and
applying a first control voltage to the first electroactive element of the warpage control carrier to substantially flatten the panel.

12. The method of claim 11 , further comprising forming a planar-sensitive layer over the plurality of semiconductor die at the active side of the panel while the panel is substantially flattened on the warpage control carrier.

13. The method of claim 11 , wherein the warpage control carrier further includes a sensor element configured to provide an output voltage indicative of panel warpage while the warpage control carrier is attached to the backside of the panel.

14. The method of claim 13 , wherein the first control voltage applied to the first electroactive element is based on the output voltage of the sensor element.

15. The method of claim 11 , wherein the first control voltage applied to the first electroactive element is derived from a look-up table.

16. The method of claim 11 , wherein the warpage control carrier further includes a second electroactive element located in a region of the warpage control panel substantially different from the first electroactive element, and wherein the panel is substantially flattened while the first control voltage is applied to the first electroactive element and a second control voltage is applied to the second electroactive element.

Assignees

• Nxp Usa Inc

Inventors

• Hayes Scott M
• Vincent Michael B
• Gong Zhiwei
• Gan Richard Te
• Gupta Vivek

Classifications

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title

• H10P72/7418

  of passive members, e.g. a chip mounting substrate · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title