Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9786520-B2
Application number	US-201514937573-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Oct 2, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided.

First claim

What is claimed is:

1. A method of manufacturing a device, comprising:
providing a carrier, the carrier including a top surface;
covering a portion of the top surface with a plurality of active dies;
dispensing a first molding compound circle with a first Coefficient of Thermal Expansion (CTE) over a central region of the carrier to cover top surfaces of some of the plurality of active dies;
dispensing a second molding compound ring with a second CTE over a peripheral region of the carrier to cover top surfaces of some of the plurality of active dies; and
pressing the first molding compound circle and the second molding compound ring by an upper mold to spread the first molding compound circle and the second molding compound ring, thereby covering top surfaces of all the plurality of active dies.

2. The method of claim 1 , further comprising:
disposing a protrudent band surrounding the second molding compound ring, wherein the protrudent band includes a rim shaped along the contour of the carrier.

3. The method of claim 2 , wherein the protrudent band includes a CTE smaller than a CTE of the first molding compound circle.

4. The method of claim 2 , wherein the protrudent band includes quartz, silicon oxide, or silicon.

5. The method of claim 2 , wherein the protrudent band includes a width ranges about 2 mm to about 18 mm.

6. The method of claim 2 , wherein the protrudent band is pre-formed before being disposed over the periphery of the carrier.

7. The method of claim 2 , further comprising gluing the protrudent band over the periphery of the top surface with an adhesive.

8. The method of claim 2 , wherein the protrudent band includes an inner edge having a zigzag pattern.

9. The method of claim 2 , wherein the first molding compound circle and the second molding compound ring include a same height with the protrudent band.

10. A method of correcting warpage of a Wafer Level Packaging (WLP) semiconductor structure, comprising:
providing a carrier, the carrier including a top surface;
covering a portion of the top surface with a plurality of active dies;
disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier;
forming a CTE gradient structure radially distributed with respect to a central region of the carrier, comprising:
forming a first molding compound with a first CTE over the central region of the carrier to embed the plurality of active dies;
forming a second molding compound ring between the protrudent band and the first molding compound, wherein the second molding compound ring has a second CTE, and the second CTE is between the first CTE and a CTE of the protrudent band.

11. The method of claim 10 , wherein the second CTE is greater than the first CTE.

12. The method of claim 10 , wherein the second CTE is smaller than the first CTE.

13. The method of claim 10 , further comprising performing a thermal setting operation to mold the first molding compound and the second molding compound ring.

14. The method of claim 13 , further comprising grinding the first molding compound and the second molding compound ring to be at a same level, and the first molding compound and the second molding compound ring form a substantially flat surface with the protrudent band.

15. A method for determining a width of the protrudent band of claim 2 , comprising correlating the width of the protrudent band to Coefficient of Thermal Expansion (CTE) mismatch between components constituting the device, wherein the width of the protrudent band is determined to be increased when the CTE mismatch between the carrier and the first molding compound circle is over 3 ppm/° C. or when the CTE mismatch between the carrier and the second molding compound ring is over 3 ppm/° C.

16. The method of claim 15 , wherein the CTE mismatch between components constituting the device and the width of the protrudent band are positively correlated.

17. The method of claim 15 , wherein the width of the protrudent band is determined to be between about 5 mm and about 10 mm when the active dies pattern density is greater than 90%.

18. The method of claim 15 , wherein the width of the protrudent band is determined to be between about 8 mm and about 18 mm when the size of each of the active dies is about 20 mm×20 mm.

19. The method of claim 15 , further comprising correlating the width of the protrudent band to the active dies pattern density.

20. The method of claim 15 , further comprising correlating the width of the protrudent band to sizes of the active dies.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yu-Chih
• Huang Chang-Chia
• Lin Shih-Yen
• Chen Chin-Liang
• Ho Kuan-Lin
• Lin Wei-Ting

Classifications

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W76/47

  Solid or gel fillings · CPC title

• H10W74/016

  using moulds · CPC title