Storage devices and methods of operating storage devices

Patent metadata

Field	Value
Publication number	US-11791013-B2
Application number	US-202117382868-A
Country	US
Kind code	B2
Filing date	Jul 22, 2021
Priority date	Dec 23, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A storage device includes a plurality of nonvolatile memory devices, a storage controller circuit and a leakage detection circuit. The storage controller circuit controls a plurality of nonvolatile memory devices, the storage controller circuit includes a plurality of connection terminals, each of the plurality of connection terminals is commonly connected to a corresponding set of pins, from among the pluralities of pins included in the plurality of nonvolatile memory devices, via a corresponding connection node, from among a plurality of connection nodes. The pins included in each set of pins have a same attribute. The leakage detection circuit is configured to determine whether leakage occurs at each set of pins based on the merged signal generated by the connection node connected to each set of pins, and configured to provide the storage controller circuit with a detection signal indicating a result of the determination.

First claim

What is claimed is:

1. A storage device comprising:
a plurality of nonvolatile memory devices, each including a plurality of pins;
a storage controller circuit configured to control the plurality of nonvolatile memory devices, wherein the storage controller circuit includes a plurality of connection terminals, each of the plurality of connection terminals is commonly connected to a corresponding set of pins, from among the pluralities of pins included in the plurality of nonvolatile memory devices, via a corresponding connection node, from among a plurality of connection nodes, wherein the pins included in each set of pins have a same attribute, and wherein each connection node from among the plurality of connection nodes is configured to generate a merged signal by merging a plurality of signals; and
a leakage detection circuit configured to determine whether leakage occurs at each set of pins based on the merged signal generated by the connection node connected to each set of pins, and configured to provide the storage controller circuit with a detection signal indicating a result of the determination,
wherein the storage controller circuit includes a register and is further configured to,
store leakage information on whether the leakage occurs at each set of pins in the register, and
change an operation mode of the plurality of nonvolatile memory devices based on leakage information.

2. The storage device of claim 1 ,
wherein the storage controller circuit, the plurality of nonvolatile memory devices and the leakage detection circuit are on a printed circuit board (PCB), and
wherein the leakage detection circuit comprises:
a detector circuit connected to a first node, the detector circuit configured to generate the detection signal based on the merged signal generated by a connection node from among the plurality of connection nodes; and
a plurality of selection transistors connected in parallel between the plurality of connection nodes and the first node, and
wherein the storage controller circuit is further configured to turn on the plurality of selection transistors sequentially in response to a plurality of turn-on voltages.

3. The storage device of claim 2 , wherein the detector circuit further comprises:
a sensing resistor coupled between a voltage node and the first node;
a comparator configured to output the detection signal by sequentially comparing a reference voltage with a merged signal generated by one of the plurality of connection nodes;
a multiplexer connected to a voltage terminal; and
a voltage supplier circuit configured to provide a first voltage and a ground voltage to the multiplexer and configured to provide the reference voltage to the comparator, based on an operating voltage,
wherein the multiplexer is configured to, in response to a selection signal,
provide the first voltage to the voltage terminal in a first detection mode, and
provide the ground voltage to the voltage terminal in a second detection mode.

4. The storage device of claim 3 ,
wherein while the plurality of selection transistors are sequentially connected to the first node,
wherein, the storage controller circuit is configured to, in the first detection mode, determine internal leakage of a portion of each set of pins based one of the merged signals generated by the plurality of connection nodes, and
wherein the storage controller circuit is configured to, in the second detection mode, determine external leakage of a portion of each set of pins based on the merged signal generated by the connection node, from among the plurality of connection nodes, that is connected to each set of pins.

5. The storage device of claim 1 , wherein the storage controller circuit comprises:
a pin manager circuit including the register; and
a storage controller processor configured to control the pin manager circuit and configured to adaptively change the operation mode of the plurality of nonvolatile memory devices by referring to the register.

6. The storage device of claim 5 , wherein the leakage detection circuit includes:
a detector circuit connected to a first node, the detector circuit configured to generate the detection signal based on the merged signal; and
a plurality of selection transistors connected in parallel between the plurality of connection nodes and the first node, the storage controller circuit being further configured to selectively turn on each of the plurality of selection transistors in response to a plurality of turn-on voltages, and
wherein the pin manager circuit is configured to, based on control of the storage controller processor, sequentially enable the plurality of turn-on voltages and to apply each of the enabled turn-on voltages to a corresponding selection transistor from among the plurality of selection transistors.

7. The storage device of claim 5 ,
wherein the leakage detection circuit further comprises:
a detector circuit and
plurality of selection transistors,
wherein the plurality of selection transistors include a first selection transistor connected to a first pin from among each of the pluralities of pins of the plurality of nonvolatile memory devices at a first connection node from among the plurality of connection nodes,
wherein each first pin is configured to output a ready/busy signal, and
wherein the first selection transistor is configured to provide the detector circuit with a first merged signal in response to a first turn-on voltage among a plurality of turn-on voltages, the first merged signal being the merged signal generated by the first connection node.

8. The storage device of claim 7 , wherein:
the pin manager circuit is further configured to,
determine a leakage of the first pins based on the detection signal during the first selection transistor being turned-on, and
store leakage information associated with the first pins in the register in response to determining that the leakage occurs in at least a portion of the first pins, and

the storage controller processor is configured to change an internal operation status check of each of the nonvolatile memory devices from a first mode based on a level of the ready/busy signal to a second mode based on a command by referring to the register, the operation status check being associated with the first pin.

9. The storage device of claim 7 ,
wherein the plurality of selection transistors further include a second selection transistor and a third selection transistor,
wherein the second selection transistor is connected to a second pin from among each of the pluralities of pins of the plurality of nonvolatile memory devices at a second connection node from among the plurality of connection nodes,
wherein the second pin is configured to receive a first sub differential signal of a differential signal,
wherein the second selection transistor is configured to provide the detector circuit with a second merged signal in response to a second turn-on voltage among the plurality of turn-on voltages, the second merged signal being the merged signal generated by the second connection node,
wherein the third selection transistor is connected to a third pin from among each of the pluralities of pins of the plurality of nonvolatile memory devices at a third connection node from among the plurality of connection nodes,
wherein the third pins are configured to receive a second sub differential signal of the differential signal, and
wherein the third selection transistor is configured to provide the detector circuit with a third merged signal in response to a third turn-on voltage among the plurality of turn-on voltages, the third merged signal being the merged signal generated by the third connection node.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Seungjun
• Lee Jihwa
• Lee Kyungduk

Classifications

• G11C29/702 Primary

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C29/022 Primary

  in I/O circuitry · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title