Memory component with efficient write operations

Patent metadata

Field	Value
Publication number	US-11790973-B2
Application number	US-202117376032-A
Country	US
Kind code	B2
Filing date	Jul 14, 2021
Priority date	May 3, 2016
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

First claim

What is claimed is:

1. A memory device comprising:
a first sub-array having a plurality of sub-rows of memory elements;
a plurality of sense amplifiers associated with a plurality of memory elements;
a decoder coupled to the plurality of sense amplifiers, wherein the decoder is to:
receive a write command associated with a burst of write data;
determine that the write command is addressing an entire sub-row of a first sub-row of the plurality of sub-rows;
receive a second write command associated with a second burst of write data; and
determine that the second write command is addressing less than an entire sub-row of a second sub-row of the plurality of sub-rows; and

a write driver coupled to the first sub-array, wherein the write driver is to:
receive the burst of write data;
load the plurality of sense amplifiers with the burst of write data without previously sensing data stored at the memory elements in the first sub-row, responsive to a determination that the write command is addressing the entire sub-row of the first sub-row;
receive the second burst of write data; and
load the plurality of sense amplifiers with the second burst of write data with previously sensing the data stored at the memory elements in the second sub-row.

2. The memory device of claim 1 , wherein the write driver is further to:
load, based on a column address, the second burst of write data to a specified subset of the plurality of sense amplifiers, wherein the plurality of sense amplifiers are activated to sense the data previously stored in the memory elements in the second sub-row before the second burst of write data; and
transfer the second burst of write data and a portion of the sensed data from the plurality of sense amplifiers to the memory elements of the second sub-row.

3. The memory device of claim 1 , wherein the memory device consumes less power for the write command than the second write command.

4. The memory device of claim 1 , further comprising a wordline driver, coupled to the first sub-array, to assert a wordline for the first sub-row after the burst of write data is loaded into the plurality of sense amplifiers, wherein asserting the wordline transfers the burst of write data from the plurality of sense amplifiers to the memory elements of the first sub-row.

5. The memory device of claim 1 , wherein a row address and a column address for the write command are provided as a single command.

6. The memory device of claim 1 , further comprising:
a first memory bank comprising the first sub-array and a second sub-array; and
a wordline driver coupled to the first memory bank.

7. The memory device of claim 1 , wherein the memory device is operable at a temperature of less than 80 Kelvin.

8. The memory device of claim 1 , further comprising a plurality of column lines operatively coupled to the plurality of memory elements.

9. The memory device of claim 8 , wherein the plurality of column lines are routed over the plurality of memory elements.

10. A method of operating a memory device, the method comprising:
receiving a write command associated with a burst of write data;
determining that the write command is addressing an entire sub-row of a first-sub row of a plurality of sub-rows of memory elements;
receiving the burst of write data;
loading a plurality of sense amplifiers with the burst of write data without previously sensing data stored at the memory elements in the first sub-row, responsive to a determination that the write command is addressing the entire sub-row of the first sub-row;
receiving a second write command associated with a second burst of write data;
determining that the second write command is addressing less than an entire sub-row of a second sub-row of the plurality of sub-rows;
receiving the second burst of write data; and
loading the plurality of sense amplifiers with the second burst of write data with previously sensing the data stored at the memory elements in the second sub-row.

11. The method of claim 10 , further comprising asserting, by a wordline driver, a wordline for the first sub-row after the burst of write data is loaded into the plurality of sense amplifiers, wherein asserting the wordline transfers the burst of write data from the plurality of sense amplifiers to the memory elements of the first sub-row.

12. The method of claim 11 , further comprising pre-charging a plurality of bitlines associated with the first sub-row after the wordline is asserted.

13. The method of claim 10 , further comprising determining that the write command is writing to each element of the plurality of memory elements based on a write activation signal indicating a write operation.

14. The method of claim 10 , further comprising:
receiving a second write command to write a second burst of write data to a second sub-row;
activating a second plurality of sense amplifiers for the second sub-row to sense stored data in a second plurality of memory elements;
loading the second burst of write data to the second plurality of sense amplifiers; and
transferring second data from the second plurality of sense amplifiers to the second plurality of memory elements.

15. The method of claim 10 , further comprising:
receiving a second write command to write a second burst of write data to a second sub-row;
determining that the second write command is writing to less than all memory elements of the second sub-row based on a second write activation signal indicating an operation;
asserting a wordline for the second sub-row to sense data stored in a second plurality of memory elements to a second plurality of sense amplifiers associated with the second plurality of memory elements;
loading, based on a column address, the second burst of write data to the second plurality of sense amplifiers; and
transferring the second burst of write data from the plurality of sense amplifiers to the plurality of memory elements.

16. A method comprising:
receiving a write command associated with a first burst of write data;
determining that the write command is addressing an entire sub-row of a first-sub row of a memory array;
loading a first plurality of sense amplifiers with the first burst of write data without previously sensing data stored at memory elements in the first sub-row, responsive to a determination that the write command is addressing the entire sub-row of the first sub-row;
transferring the first burst of write data from the first plurality of sense amplifiers to the first-sub row;
receiving a second write command to write a second burst of write data to a second sub-row of the memory array;
loading, responsive to the second write command, a second plurality of sense amplifiers with the second burst of write data with previously sensing data stored at memory elements of the second sub-row; and
transferring the second burst of write data from the second plurality of sense amplifiers to the second sub-row.

17. The method of claim 16 , further comprising:
determining that the second write command is writing to less than all memory elements of the second sub-row based on a second write activation signal; and
asserting a wordline for the second sub-row to sense data stored in the memory elements of the second sub-row to the second plurality of sense amplifiers, wherein loading the second burst of write data comprises loading the second burst of write data based on a column address.

18. The method of claim 16 , wherein determining that the write command is addressing the entire sub-row of the first-sub row is

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Linstadt John Eric
• Haukness Brent Steven
• Wright Kenneth L
• Vogelsang Thomas

Classifications

• G11C11/403 Primary

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G06F12/06 Primary

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C7/1018

  Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title