System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit

Patent metadata

Field	Value
Publication number	US-11790035-B2
Application number	US-202117315710-A
Country	US
Kind code	B2
Filing date	May 10, 2021
Priority date	Jun 30, 2016
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A batched Cholesky decomposition method, system, and non-transitory computer readable medium for a Graphics Processing Unit (GPU), include mirroring matrices to form paired matrices solving the paired matrices simultaneously.

First claim

What is claimed is:

1. A non-transitory computer-readable recording medium recording a batched Cholesky decomposition program for a Graphics Processing Unit (GPU) having a plurality of threads that perform work, the program causing a computer to perform:
mirroring matrices;
forming paired matrices by combining a mirrored matrix of the mirrored matrices with a non-mirrored matrix; and
solving the paired matrices simultaneously by each thread of the plurality of threads of the GPU performing a same amount of work.

2. The non-transitory computer readable recording medium of claim 1 , wherein the mirroring is performed by shifting the mirrored matrix of the mirrored matrices by N+1, where N is an integer.

3. The non-transitory computer readable recording medium of claim 1 , wherein during the solving, each thread of the plurality of threads of the GPU performs an equal amount of work when running batched Cholesky decomposition program.

4. A batched Cholesky decomposition method for a Graphics Processing Unit (GPU) having a plurality of threads that perform work, the method comprising:
mirroring matrices;
forming paired matrices by combining a mirrored matrix of the mirrored matrices with a non-mirrored matrix; and
solving the paired matrices simultaneously by each thread of the plurality of threads of the GPU performing a same amount of work.

5. A batched Cholesky decomposition system on a Graphics Processing Unit (GPU) having a plurality of threads that perform work, said system comprising:
a processor; and
a memory, the memory storing instructions to cause the processor to:
mirroring matrices;
forming paired matrices by combining a mirrored matrix of the mirrored matrices with a non-mirrored matrix; and
solving the paired matrices simultaneously by each thread of the plurality of threads of the GPU performing a same amount of work.

Assignees

• IBM

Inventors

• Cho Minsik
• Kung David Shing-Ki
• Puri Ruchir

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F5/015

  having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · CPC title

• G06F17/12

  Simultaneous equations {, e.g. systems of linear equations} · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title