Capacitive pressure difference sensor with improved bonding and manufacturing method

Patent metadata

Field	Value
Publication number	US-11788914-B2
Application number	US-202318109357-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	Feb 14, 2022
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

Provided are a pressure difference sensor, and a manufacturing method and an application thereof. A manner of bonding three layers of wafers is adopted, and the sensor includes an upper structure, an intermediate structure and a lower structure. Each of the upper structure and the intermediate structure is manufactured by a silicon-on-insulator (SOI) wafer, the lower structure is manufactured by patterned doped intrinsic silicon; and a lead pad of each of the upper electrode, and the intermediate electrode and the lower electrode is located on a corresponding one of three-stepped steps at a side of the pressure difference sensor. Annular through holes are formed around the upper electrode and the lower electrode. A constant capacitance of a capacitance signal outputted by an upper capacitor of the sensor by extending an electric field line path of the constant capacitor part.

First claim

What is claimed is:

1. A pressure difference sensor, manufactured by a manner of bonding three layers of wafers, and comprising: an upper structure, an intermediate structure and a lower structure;
wherein each of the upper structure and the intermediate structure is manufactured by a silicon-on-insulator (SOI) wafer, and the lower structure is manufactured by patterned doped intrinsic silicon;
wherein an upper electrode, an intermediate electrode and a lower electrode are respectively arranged on the upper structure, the middle structure and the lower structure, and a lead pad of each of the upper electrode, the intermediate electrode and the lower electrode is located on a corresponding one of three-stepped steps at a side of the pressure difference sensor;
wherein annular through holes are formed around the upper electrode and the lower electrode; the pressure difference sensor is made by cutting the three layers of wafers after bonding of the three layers of wafers, and a manner of the bonding is metal eutectic bonding;
wherein the metal eutectic bonding comprises an upper metal bonding layer and a lower metal bonding layer, an upper portion of the upper metal bonding layer comes from an upper wafer and a lower portion of the upper metal bonding layer comes from an intermediate wafer; and an upper portion of the lower metal bonding layer comes from an intermediate wafer and a lower portion of the lower metal bonding layer comes from a lower wafer;
wherein the upper electrode is located in the upper structure, and is formed by processing the upper wafer; the intermediate electrode is located in the intermediate layer structure, and is formed by processing the intermediate wafer; the lower electrode is located in the lower structure;
wherein a pressure guide hole in the upper structure and a pressure guide hole in the lower structure are arranged to be surround the upper electrode and the lower electrode respectively;
wherein the upper structure is made by processing the SOI wafer, an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, a lower silicon part of the SOI wafer is heavily doped silicon, and the upper electrode is derived from the heavily doped silicon of the lower silicon part of the SOI wafer;
wherein the intermediate structure is made by processing the SOI wafer, an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, a lower silicon part of the SOI wafer is heavily doped silicon, and the intermediate electrode is derived from the heavily doped silicon of the lower silicon part of the SOI wafer; and the lead pad of the intermediate electrode is configured to connect the intermediate electrode to an external circuit;
wherein the lower structure is made by processing an intrinsic silicon wafer with a high resistivity, the lower electrode is made through patterned doping of the wafer, a circular portion of a doped part plays the role of a capacitor plate, a bottom rectangle portion of the doped part is configured to make ohmic contact with the lead pad of the lower electrode, and a portion between the circular portion and the bottom rectangle portion is a lead portion, which is responsible for realizing the electrical connection between the circular portion and the bottom rectangle portion;
wherein a spacing between the lower electrode and the intermediate electrode is composed of three parts comprising: silicon dioxide having supporting and insulating functions on a lower surface of the intermediate structure, the lower metal bonding layer, and silicon dioxide having supporting and insulating functions on an upper surface of the lower structure; and
wherein a thickness of the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure is in a range from 0 to 3 μm, a thickness of the lower metal bonding layer is in a range from 0 to 4 μm, a thickness of the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure is in a range from 0 to 3 μm, and a sum of the three thicknesses is no more than 10 μm.

2. A manufacturing method of a sensor comprising the pressure difference sensor according to claim 1 , wherein the method comprises process flows for manufacturing the upper structure, the intermediate structure and the lower structure;
wherein the process flow for manufacturing the upper structure comprises:
step 1, etching the pressure guide hole, a lead hole, an upper step hole, aligning marks and cutting marks located in the upper structure;
step 2, performing etching a lower surface to form a boss to prepare for manufacturing the upper electrode;
step 3, removing a silicon dioxide layer exposed after etching the lower surface;
step 4, forming an insulating silicon dioxide layer on a surface of the wafer, that is, the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure, and the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure;
step 5, exposing the upper electrode on the upper surface to prepare for a consequent lead;
step 6, preparing for manufacturing a portion of the upper metal bonding layer located in the upper structure; and
step 7, manufacturing the portion of the upper metal bonding layer located in the upper structure;
wherein the process flow for manufacturing the intermediate structure comprises:
step 1, forming silicon dioxide on a surface to: prepare for forming silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure and silicon dioxide having supporting and insulating functions on the upper surface of an intermediate structure; and prepare for forming a portion of the upper metal bonding layer located in the intermediate structure, a portion of the lower metal bonding layer located in the intermediate structure, and the lead pad of the lower electrode;
step 2, removing silicon dioxide on a surface of a portion to be etched;
step 3, forming a cutting hole and the intermediate-layer movable diaphragm; and
step 4, removing the photoresist;
wherein the process flow for manufacturing the lower structure comprises:
step 1: forming the lower electrode;
step 2: forming silicon dioxide on a surface of the lower structure to prepare for the subsequent processing, and reducing a roughness of the surface and improving a flatness of the surface;
step 3: forming the pressure guide hole in the lower structure to expose the lower electrode;
step 4, forming a silicon dioxide insulating layer on an exposed surface of the lower electrode;
step 5, exposing doped silicon under the lead pad of the lower electrode;
step 6, sputtering metal to prepare for forming a portion of the lower metal bonding layer located in the lower structure and the lead pad of the lower electrode; and
step 7: forming a portion of the lower metal bonding layer located in the lower surface and the lead pad 25 of the lower electrode.

3. A design method of a Micro-Electro-Mechanical Systems (MEMS) contact capacitive pressure difference sensor comprising the pressure difference sensor according to claim 1 , and the method comprising:
(1) for a patterned constant electrode and a lead circuit thereof manufactured by a doping process, using ion implantation used to complete deep doping of a high dose and a high voltage for the electrode; after that, completing wet oxidation and planarization of a silicon wafer, and partially corroding a silicon oxide layer to expose a patterned part of the electrode; wherein the reason for the planarization operation is that an oxidation rate of a doped part is higher, resulting in a surface of

Assignees

• Langfang Zhichi Power Tech Ltd
• Univ Beihang

Inventors

• Xu tiantong
• Li Haiwang
• Tao Zhi
• Cao Xiaoda
• Zhai Yanxin
• Yang Chunhui
• Lu Haonan
• An Di
• Wang Hengyi
• Wang Zhiyang
• Zhu Kaiyun
• Fang Weidong
• Wang Wenbin
• Lei Kaibo
• Xiao Wensong
• Li Murun
• Zhang Xiao
• Feng Yang

Classifications

• G01L9/12 Primary

  by making use of variations in capacitance {, i.e. electric circuits therefor} · CPC title

• G01L9/0048

  Details about the mounting of the diaphragm to its support or about the diaphragm edges, e.g. notches, round shapes for stress relief · CPC title

• G01L13/026 Primary

  involving double diaphragm · CPC title

• G01L19/0618

  Overload protection · CPC title

• B81B7/02

  containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title